講員：台積電_王奕處長

講題：Memory for High Performance Computing in the Big Data Era

日期：111年6月16日(四) 13:30～15:00

主持人：范銘彥 教授

視訊連結：請見下方Microsoft Teams會議連結

講者介紹：
【王奕處長】
目前任職於台積電DTP | MSD | AMDT處長，專注在記憶體technology-circuit co-design。任職於台積電之前，王奕在美國Intel工作多年，專注於SRAM，embedded DRAM，emerging memory等技術的開發。其成果多次刊登在IEEE ISSCC，VLSI，IEDM，以及JSSC。

摘要：The growing disparity between CPU speed and memory speed, known as the memory wall challenge, has been one of the most critical and long-standing challenges in the computing industry. The situation is further complicated by the rapid development of complex and heterogeneous memory systems for high-performance computing and data-intensive applications, which is becoming deeper and more diversified with the adoption of new architectures and memory technologies, including the high-speed cache memory, 3D-stacked cache memory, 3D-stacked high-bandwidth DRAM etc. This seminar will discuss the trends and challenges of a variety of memories in development as well as the opportunities lying ahead to address the challenges.


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