NCKU EE 教師個人頁面
English Version
高國興 副教授
地址
奇美系館4樓95402室
TEL
+886-6-2757575 ext.62419
實驗室網站連結
K LAB
(R95A06/ext.62400-2206)
學經歷
學歷
2013
PhD, Electrical Engineering, KULeuven, Belgium
2008
MS, Electrophysics, National Chiao Tung University, Taiwan
2005
BS, Physics, National Chung Hsing University, Taiwan
經歷
2019~2022
Visiting Scholar, quantum computing, imec/KULeuven, Belgium
2018~now
Associate Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan
2015~2020
Assistant Researcher (Joint Appointment), NCHC of NARLabs, Taiwan
2014~2017
Assistant Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan
2009-2013
PhD researcher, Inter-university Microelectronic Centre (imec), Belgium
研究領域
  • Semiconductor Physics and Devices
著作
期刊論文( Journal )
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  1. K.-H. Kao*, et al., “Subthreshold Swing Saturation of Nanoscale MOSFETs Due to Source-to-Drain Tunneling at Cryogenic Temperatures”, IEEE Electron Device Lett., 41, 1296, 2020.
  2. P.-J. Sung, S.-W. Chang, K.-H. Kao, et al., “Fabrication of Vertically Stacked Nanosheet Junctionless Filed-Effect Transistors and Applications for the CMOS and CFET Inverters”, IEEE Trans. Electron Devices, 67, 3504, 2020.
  3. S.-H. Chen, S.-W. Lian, T.-R. Wu, T.-R. Chang, J.-M. Liou, D. D. Lu, K.-H. Kao*, et al., “Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs”, IEEE Trans. Electron Devices, 66, 2509, 2019.
  4.  K. Kumar, Y.-F. Hsieh, J.-H. Liao, K.-H. Kao*, et al., “Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation”, IEEE Trans. Electron Devices, 65, 4709, 2018.
  5.  V. Kumar M P, J-Y Lin, K.-H. Kao, et al., “Junctionless FETs with a Fin Body for Multi-VTH and Dynamic Threshold Operation”, IEEE Trans. Electron Devices, 65, 3535, 2018.
  6.  Y.-F. Hsieh*, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D. D. Lu and K.-H. Kao*, “A Transistor with a Source Tunneling Barrier Showing Suppressed Short Channel Effects for Low Power Applications Based on NEGF Simulation”, IEEE Trans. Electron Devices, submitted.
  7.   V. Kumar M P, C.-Y. Hu, A. M. Walke, K.-H. Kao*, et al., “Improving the Electrical Performance of a Shell Doping Profile Quantum Well Transistor by Heterojunction Optimization”, IEEE Trans. Electron Devices, 64, 3563, 2017.
  8. L. Y. Chen, Y.-F. Hsieh and K.-H. Kao*, “Undoped and Doped Junctionless FETs: Source/Drain Contacts and Immunity to Random Dopant Fluctuation”, IEEE Electron Device Lett., accepted, 2017.
  9. K.-H. Kao*, et al., “A Dopingless FET with Metal-Insulator-Semiconductor Contacts”, IEEE Electron Device Lett., 38, 5, 2017.
  10. V. Kumar M P, C.-Y. Hu, K.-H. Kao*, et al., “Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs”, IEEE Trans. Electron Devices, 62, 3541, 2015.
  11. K.-H. Kao, et al.,“Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors”, J. Appl. Phys., 116, 214506,214
  12. K.-H. Kao, et al. “Tensile strained Ge tunnel field-effect transistors: k·p material modeling and numerical device simulation”, J. Appl. Phys., 115, 044505, 2014.
  13. A. M. Walke, A. Vandooren, R. Rooyackers, D. Leonelli, D. Hikavy, R. Loo, A. S. Verhulst, K.-H. Kao, et al., “Fabrication and analysis of a Si/Si0.55Ge0.45 hetero-junction line tunnel FET”,IEEE Trans. ElectronDevices., 61, 707, 2014.
  14. A. M. Walke, W. G. Vandenberghe, K.-H. Kao, et al., “A simulation study on process sensitivity of a line tunnel field-effect transistor”, IEEE Trans. Electron Devices, vol. 60, 1019, 2013.
  15. D. Verreck, A. S. Verhulst, K.-H. Kao, et al., “Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors”, IEEE Trans. Electron Devices, vol. 60, 2128, 2013.
  16. K.-H. Kao, et al., “Counter-doped pocket thickness optimization of gate-on-source-only tunnel FETs”, IEEE Trans. Electron Devices, vol. 60, p. 6-12, 2013.
  17. K.-H. Kao, et al., “Optimization of gate-on-source-only tunnel FETs with counter-doped pockets”, IEEE Trans. Electron Devices, vol. 59, p. 2070-2077, 2012.
  18. K.-H. Kao, et al., “Direct and indirect band-to-band tunneling in germanium-based TFETs,” IEEE Trans. Electron Devices, vol. 59, p. 292-301, 2012.
  19. K.-H. Kao, et al., “Modeling the impact of junction angles in tunnel field-effect transistors”, Solid State Electron., vol. 69, p. 31-37, 2012.
  20. W. G. Vandenberghe, A. S. Verhulst, K.-H. Kao, et al., “A model determining optimal doping concentration and material’s band gap of tunnel field-effect transistors,” Appl. Phys. Lett., 100, 193509, 2012.
  21. K.-H. Kao, et al., “X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method,” Appl. Phys. Lett., 93, 092907, 2008.
會議論文( Conference )
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  1. S.-W. Chang, et al., “First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications”, IEEE IEDM Tech. Dig., 11.7, 2019.
  2. Y.-T Tang, C.-L. Fan, Y.-C. Kao, N. Modolo, C.-J. Su, T.-L. Wu, K.-H. Kao, et al., “A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs”, VLSI Tech. Dig., T17-2, 2019.
  3. P.-J. Sung, C.-Y. Chang, L.-Y. Chen, K.-H. Kao, et al., “Voltage Transfer Characteristics Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs Application”, IEEE IEDM Tech. Dig., 21.4, 2018.
  4. 4. Y.-T Tang, C.-J. Su, Y.-S. Wang, K.-H. Kao, et al., “A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5nm Node”, VLSI Tech. Dig., 45, 2018.
  5. C.-J. Su, T.-C. Hong, Y.-C. Tsou, F.-J. Hou, P.-J. Sung, M.-S. Yeh, C.-C. Wan, K.-H. Kao, et al., “Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability” IEEE IEDM Tech. Dig., 15.4, 2017.
  6. C.-J. Su, Y.-T. Tang, Y.-C. Tsou, P.-J. Sung, F.-J. Hou, C.-J. Wang, S.-T. Chung, C.-Y. Hsieh, Y.-S. Yeh, F.-K. Hsueh, K.-H. Kao, et al., “Nano-scaled Ge FinFETs with Low Temperature Ferroelectric HfZrOx on Specific Interfacial Layers Exhibiting 65% S.S. Reduction and Improved ION” VLSI Tech. Dig., T12-1, 2017.
  7. Y.-J. Lee, T.-C. Hong, F.-K. Hsueh, P.-J. Sung, C.-Y. Chen, S.-S. Chang, T.-C. Cho, S. Noda, Y.-C. Tsou, K.-H. Kao, et al., “High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications”, IEEE IEDM Tech. Dig., 33.5, 2016.
  8. Y.-J. Lee, F.-J. Hou, S.-S. Chang, F.-K. Hsueh, K.-H. Kao, et al., “Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology”, IEEE IEDM Tech. Dig., 15.1, 2015.
  9. Y.-J. Lee, T.-C. Cho, P.-J Sung, K.-H. Kao, et al., “High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications”, IEEE IEDM Tech. Dig., 6.2, 2015.
  10. Y.-J. Lee, T.-C. Cho, K.-H. Kao, et al., “A Novel Junctionless FinFET Structure with sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing”, IEEE IEDM Tech. Dig., 32.7, 2014.
  11. A. S. Verhulst, D. Verreck, Q. Smets, K.-H. Kao, et al., “Perspective of Tunnel-FET for Future Low-Power Technology Nodes”, IEEE IEDM Tech. Dig., 30.2, 2014 (invited)
  12. W.-C. Wu, C.-S. Lai, S.-C. Lee, M.-W. Ma, T.-S. Chao, J.-C. Wang, C.-W. Hsu, P.-C. Chou, J.-H. Chen, K.-H. Kao, et al., “Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation,” IEDM Tech. Dig., 405, 2008.
專利
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  1. Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method. United States patent, No. 7460550, Dec. 2008
  2. A. S. Verhulst and K.-H. Kao, 2012, "Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method" USA Patent No. 20120298959 A1
其他
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其他
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研究計劃
  1. 量子電子元件與人工智慧於半導體產業之應用 : 機器學習導向之量子傳輸模擬及與現今半導體製程相容之新穎元件製作(2018-2023)
  2. 無摻雜場效電晶體: 非平衡態格林函數量子傳輸模擬與實驗(2017-2019)
  3. 空乏型量子井場效電晶體(2016-2017)
  4. 具殼層淺參雜(深度小於5奈米且陡峭度 ~ 0.7奈米每10倍變化)之量子電子元件於節能電子的應用(I) (2015-2016)
  5. 型變鍺錫量子穿隧電晶體之物理模型與元件模擬(2014-2015)
開授課程
103 Academic year 2
105 Academic year 1
106 Academic year 1
107 Academic year 1
指導學生
本學年度 實驗室成員
博士班
Ankit Agarwal
碩士班
林士翔
呂銘皓
瞿廷仰
柳安澤
方秉宏
黃勝義
趙浩宇
駱俊翔
謝武聰
張群耀
吳承翰
傅柏元
邱子恩
何承奕
李益誠
孫苡翔
已畢業學生
特殊榮譽
  1. 2014 IEEE Tainan Section Best Ph.D. Thesis Award
  2. 2015 NARLabs Superior Technical Achievement Award
  3. 2017 TSIA Award for Young Researcher with Doctoral Degree
  4. 2018 MOST Young Scholar Fellowship
  5. 2019吳大猷獎
  6. 2019 NARLabs Excellent Technical Achievement Award