啟端館3樓96308室
高國興 教授
學經歷
學歷
2013
PhD, Electrical Engineering, KULeuven, Belgium
2008
MS, Electrophysics, National Chiao Tung University, Taiwan
2005
BS, Physics, National Chung Hsing University, Taiwan
經歷
2014~now
Assistant Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan
2009-2013
PhD researcher, Inter-university Microelectronic Centre (imec), Belgium
研究領域
- Semiconductor Physics and Devices
著作
期刊論文( Journal )
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- K. Kumar, Y.-F. Hsieh, J.-H. Liao, K.-H. Kao*, et al., “Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation”, IEEE Trans. Electron Devices, 65, 4709, 2018.
- V. Kumar M P, J-Y Lin, K.-H. Kao, et al., “Junctionless FETs with a Fin Body for Multi-VTH and Dynamic Threshold Operation”, IEEE Trans. Electron Devices, 65, 3535, 2018.
- Y.-F. Hsieh*, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D. D. Lu and K.-H. Kao*, “A Transistor with a Source Tunneling Barrier Showing Suppressed Short Channel Effects for Low Power Applications Based on NEGF Simulation”, IEEE Trans. Electron Devices, submitted.
會議論文( Conference )
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- P.-J. Sung, C.-Y. Chang, L.-Y. Chen, K.-H. Kao, et al., “Voltage Transfer Characteristics Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs Application”, IEEE IEDM Tech. Dig., accepted, 2018.
- Y.-T Tang, C.-J. Su, Y.-S. Wang, K.-H. Kao, et al., “A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5nm Node”, VLSI Tech. Dig., 45, 2018.
- C.-J. Su, T.-C. Hong, Y.-C. Tsou, F.-J. Hou, P.-J. Sung, M.-S. Yeh, C.-C. Wan, K.-H. Kao, et al., “Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability” IEEE IEDM Tech. Dig., 2017, accepted.
專利
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- Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method. United States patent, No. 7460550, Dec. 2008
- A. S. Verhulst and K.-H. Kao, 2012, "Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method" USA Patent No. 20120298959 A1
其他
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研究計劃
- 無摻雜場效電晶體: 非平衡態格林函數量子傳輸模擬與實驗(2017-2019)
- 空乏型量子井場效電晶體(2016-2017)
- 具殼層淺參雜(深度小於5奈米且陡峭度 ~ 0.7奈米每10倍變化)之量子電子元件於節能電子的應用(I) (2015-2016)
- 型變鍺錫量子穿隧電晶體之物理模型與元件模擬(2014-2015)
開授課程
103學年度下學期
105學年度上學期
106學年度上學期
107學年度上學期
指導學生
本學年度 實驗室成員
博士班
Ankit Agarwal
碩士班
謝武聰
張群耀
吳承翰
傅柏元
邱子恩
何承奕
李益誠
孫苡翔
孫琮傑
鐘子軒
陳君書
黃渟詒
黃宣博
黃楷文
林峻佑
陳柏碩
林瑋晟
已畢業學生
特殊榮譽
- IEEE Tainan Section 2014 Best Ph.D. Thesis Award
- 2015 NARLabs Superior Technical Achievement Award
- 2017 TSIA Award for Young Researcher with Doctoral Degree
- 2018 MOST Young Scholar Fellowship
- 2020台灣電子材料與元件協會-傑出青年獎
- 2021台灣國家實驗研究院-研發服務平台亮點成果獎