NCKUEE Faculty Data
Chinese Version
Professor Kuo-Hsing Kao
Address
ChiMei Building 4F R95402
Email
TEL
+886-6-2757575 ext.62419
Lab Weblink
KLAB
(R95A06/ext.62400-2206)
Background
Educations
2013
PhD, Electrical Engineering, KULeuven, Belgium
2008
MS, Electrophysics, National Chiao Tung University, Taiwan
2005
BS, Physics, National Chung Hsing University, Taiwan
Experiences
2014~now
Assistant Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan
2009-2013
PhD researcher, Inter-university Microelectronic Centre (imec), Belgium
Specialities
  • Semiconductor Physics and Devices
Publication
Journal
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  1.  K. Kumar, Y.-F. Hsieh, J.-H. Liao, K.-H. Kao*, et al., “Significance of Multivalley and Nonparabolic Band Structure for GeSn TFET Simulation”, IEEE Trans. Electron Devices, 65, 4709, 2018.
  2.  V. Kumar M P, J-Y Lin, K.-H. Kao, et al., “Junctionless FETs with a Fin Body for Multi-VTH and Dynamic Threshold Operation”, IEEE Trans. Electron Devices, 65, 3535, 2018.
  3.  Y.-F. Hsieh*, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D. D. Lu and K.-H. Kao*, “A Transistor with a Source Tunneling Barrier Showing Suppressed Short Channel Effects for Low Power Applications Based on NEGF Simulation”, IEEE Trans. Electron Devices, submitted.
  4.   V. Kumar M P, C.-Y. Hu, A. M. Walke, K.-H. Kao*, et al., “Improving the Electrical Performance of a Shell Doping Profile Quantum Well Transistor by Heterojunction Optimization”, IEEE Trans. Electron Devices, 64, 3563, 2017.
  5. L. Y. Chen, Y.-F. Hsieh and K.-H. Kao*, “Undoped and Doped Junctionless FETs: Source/Drain Contacts and Immunity to Random Dopant Fluctuation”, IEEE Electron Device Lett., accepted, 2017.
  6. K.-H. Kao*, et al., “A Dopingless FET with Metal-Insulator-Semiconductor Contacts”, IEEE Electron Device Lett., 38, 5, 2017.
  7. V. Kumar M P, C.-Y. Hu, A. M. Walke, K.-H. Kao*, et al., “Improving the Electrical Performance of a Shell Doping Profile Quantum Well Transistor by Heterojunction Optimization”, IEEE Trans. Electron Devices, accepted.
  8. V. Kumar M P, C.-Y. Hu, K.-H. Kao*, et al., “Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs”, IEEE Trans. Electron Devices, 62, 3541, 2015.
  9. K.-H. Kao, et al.,“Compressively strained SiGe band-to-band tunneling model calibration based on p-i-n diodes and prospect of strained SiGe tunneling field-effect transistors”, J. Appl. Phys., 116, 214506,214
  10. K.-H. Kao, et al. “Tensile strained Ge tunnel field-effect transistors: k·p material modeling and numerical device simulation”, J. Appl. Phys., 115, 044505, 2014.
  11. A. M. Walke, A. Vandooren, R. Rooyackers, D. Leonelli, D. Hikavy, R. Loo, A. S. Verhulst, K.-H. Kao, et al., “Fabrication and analysis of a Si/Si0.55Ge0.45 hetero-junction line tunnel FET”,IEEE Trans. ElectronDevices., 61, 707, 2014.
  12. A. M. Walke, W. G. Vandenberghe, K.-H. Kao, et al., “A simulation study on process sensitivity of a line tunnel field-effect transistor”, IEEE Trans. Electron Devices, vol. 60, 1019, 2013.
  13. D. Verreck, A. S. Verhulst, K.-H. Kao, et al., “Quantum mechanical performance predictions of p-n-i-n versus pocketed line tunnel field-effect transistors”, IEEE Trans. Electron Devices, vol. 60, 2128, 2013.
  14. K.-H. Kao, et al., “Counter-doped pocket thickness optimization of gate-on-source-only tunnel FETs”, IEEE Trans. Electron Devices, vol. 60, p. 6-12, 2013.
  15. K.-H. Kao, et al., “Optimization of gate-on-source-only tunnel FETs with counter-doped pockets”, IEEE Trans. Electron Devices, vol. 59, p. 2070-2077, 2012.
  16. K.-H. Kao, et al., “Direct and indirect band-to-band tunneling in germanium-based TFETs,” IEEE Trans. Electron Devices, vol. 59, p. 292-301, 2012.
  17. K.-H. Kao, et al., “Modeling the impact of junction angles in tunnel field-effect transistors”, Solid State Electron., vol. 69, p. 31-37, 2012.
  18. W. G. Vandenberghe, A. S. Verhulst, K.-H. Kao, et al., “A model determining optimal doping concentration and material’s band gap of tunnel field-effect transistors,” Appl. Phys. Lett., 100, 193509, 2012.
  19. K.-H. Kao, et al., “X-ray photoelectron spectroscopy energy band alignment of spin-on CoTiO3 high-k dielectric prepared by sol-gel spin coating method,” Appl. Phys. Lett., 93, 092907, 2008.
  20. Y. Fang, W.-J. Lee, A.-C. Yang, G.-P. Chen, N.-Y. Chen and K.-H. Kao*, et al., “Inherent Dipole Layer Formation Driven by Surface Energy at Nonplanar Dielectric Interfaces”, IEEE Trans. Electron Devices, 68, 294, 2021.
Conference
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  1.     P.-J. Sung, C.-Y. Chang, L.-Y. Chen, K.-H. Kao, et al., “Voltage Transfer Characteristics Matching by Different Nanosheet Layer Numbers of Vertically Stacked Junctionless CMOS Inverter for SoP/3D-ICs Application”, IEEE IEDM Tech. Dig., accepted, 2018.
  2.   Y.-T Tang, C.-J. Su, Y.-S. Wang, K.-H. Kao, et al., “A Comprehensive Study of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Layer Effects on Negative Capacitance FETs for Sub-5nm Node”, VLSI Tech. Dig., 45, 2018.
  3.  C.-J. Su, T.-C. Hong, Y.-C. Tsou, F.-J. Hou, P.-J. Sung, M.-S. Yeh, C.-C. Wan, K.-H. Kao, et al., “Ge Nanowire FETs with HfZrOx Ferroelectric Gate Stack Exhibiting SS of Sub-60 mV/dec and Biasing Effects on Ferroelectric Reliability” IEEE IEDM Tech. Dig., 2017, accepted.
  4.   C.-J. Su, Y.-T. Tang, Y.-C. Tsou, P.-J. Sung, F.-J. Hou, C.-J. Wang, S.-T. Chung, C.-Y. Hsieh, Y.-S. Yeh, F.-K. Hsueh, K.-H. Kao, et al., “Nano-scaaled Ge FinFETs with Low Temperature Ferroelectric HfZrOx on Specific Interfacial Layers Exhibiting 65% S.S. Reduction and Improved ION” VLSI Tech. Dig., T12-1, 2017.
  5.  L.-Y. Chen, Y.-F. Hsieh and K.-H. Kao, “Undoped SiGe FETs with Metal-Insulator-Semiconductor Contacts, Silicon Nanoelectronics Workshop, submitted, 2017.
  6. Y.-J. Lee, T.-C. Hong, F.-K. Hsueh, P.-J. Sung, C.-Y. Chen, S.-S. Chang, T.-C. Cho, S. Noda, Y.-C. Tsou, K.-H. Kao, et al., “High Performance Complementary Ge Peaking FinFETs by Room Temperature Neutral Beam Oxidation for Sub-7 nm Technology Node Applications”, IEEE IEDM Tech. Dig., 33.5, 2016.
  7.    Y.-J. Lee, F.-J. Hou, S.-S. Chang, F.-K. Hsueh, K.-H. Kao, et al., “Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology”, IEEE IEDM Tech. Dig., 15.1, 2015.
  8. Y.-J. Lee, T.-C. Cho, P.-J Sung, K.-H. Kao, et al., “High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications”, IEEE IEDM Tech. Dig., 6.2, 2015.
  9. Y.J. Lee, T.C. Cho, K. H. Kao, et al., “A Novel Junctionless FinFET Structure with sub-5nm Shell Doping Profile by Molecular Monolayer Doping and Microwave Annealing”, IEEE IEDM Tech. Dig., 32.7.1-4, 2014.
  10. A.S. Verhulst, D. Verreck, Q. Smets, K. H. Kao, et al., “Perspective of Tunnel-FET for Future Low-Power Technology Nodes”, IEEE IEDM Tech. Dig., 30.2.1-4, 2014 (invited).
  11. Q. Smets, A. S. Verhulst, R. Rooyackers, C. Merckling, D. Lin, E. Simoen, A. Alian, M. Cantoro, A. Pourghaderi, K.-H. Kao, et al., “InGaAs diodes for band-to-band tunneling calibration and n- and p- lineTFET performance prediction”, SSDM, 752-753,2013
  12. A. S. Verhulst, W. G. Vandenberghe, K.-H. Kao, et al., “Tunnel field-effect transistors for low-power nano-electronics”, 2013 9th international nanotechnology conference on communication and cooperation, Berlin, Germany.
  13. A. Vandooren, A. S. Verhulst, R. Rooyackers, A. M. Walke, K.-H. Kao, et al., “Trends and challenges in tunnel field effect transistors”, “2013 7th international workshop “functional nanomaterials and devices for electronics, sensors, energy harvesting”, Ukraine.
  14. K.-H. Kao, et al., “SiGe band-to-band tunneling calibration based on p-i-n diodes: fabrication, measurement and simulation”, ECS Transactions, 50, 965-970, 2012.
  15. K.-H. Kao, et al., “The impact of junction angle on tunnel FETs”, Proceedings of Ultimate Integration on Silicon (ULIS), p. 80-83, 2011.
  16. A. S. Verhulst, W. G. Vandenberghe, D. Leonelli, R. Rooyackers, A. Vandooren, J. Zhuge, K.-H. Kao, et al., “Si-based tunnel field-effect transistors for low-power nano-electronics”, DRC, 193, 2011.
  17. W.-C. Wu, C.-S. Lai, S.-C. Lee, M.-W. Ma, T.-S. Chao, J.-C. Wang, C.-W. Hsu, P.-C. Chou, J.-H. Chen, K.-H. Kao, et al., “Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation,” IEDM Tech. Dig., 405, 2008.
  18. K.-H. Kao, et al., “Characterization of CoTiO3 Thin Films Formed by Sol-Gel Spin Coating with High Temperature Annealing”, SNDT 2007 Symposium on Nano Device Technology, Taiwan.
  19. C.-J. Su, et al., “3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T1R Configuration Demonstrated on Full Wafers”, IEEE IEDM Tech. Dig., 12.2.1, 2020.
  20. T.-Z. Hong, et al., “First Demonstration of Heterogeneous Complementary FETs Utilizing Low-Temperature (200 oC) Hetero-Layers Bonding Technique (LT-HBT)”, IEEE IEDM Tech. Dig., 15.5.1, 2020.
Patent
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  1. Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method. United States patent, No. 7460550, Dec. 2008
  2. A. S. Verhulst and K.-H. Kao, 2012, "Line-tunneling tunnel field-effect transistor (tfet) and manufacturing method" USA Patent No. 20120298959 A1
Others
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Projects
  1. 無摻雜場效電晶體: 非平衡態格林函數量子傳輸模擬與實驗(2017-2019)
  2. 空乏型量子井場效電晶體(2016-2017)
  3. 具殼層淺參雜(深度小於5奈米且陡峭度 ~ 0.7奈米每10倍變化)之量子電子元件於節能電子的應用(I) (2015-2016)
  4. 型變鍺錫量子穿隧電晶體之物理模型與元件模擬(2014-2015)
Classes
2015 Spring
2015 Fall
2016 Fall
2017 Fall
2018 Fall
Students
Current Academic Year Lab Members
Ph.D.
Ankit Agarwal
Master
謝武聰
張群耀
吳承翰
傅柏元
邱子恩
何承奕
李益誠
孫苡翔
孫琮傑
鐘子軒
陳君書
黃渟詒
黃宣博
黃楷文
林峻佑
陳柏碩
林瑋晟
Graduates of all Previous Years
Honors
  1. IEEE Tainan Section 2014 Best Ph.D. Thesis Award
  2. 2015 NARLabs Superior Technical Achievement Award
  3. 2017 TSIA Award for Young Researcher with Doctoral Degree
  4. 2018 MOST Young Scholar Fellowship
  5. 2020 Taiwan Electronics Devices and Materials Association Outstanding Young Scholar Award
  6. 2021 Taiwan NARLabs Research Service Platform highlighting Award
NCKU EE