NCKU EE 教師個人頁面
English Version
張順志 教授
地址
奇美系館5樓95507室
TEL
+886-6-2757575 ext.62380
實驗室網站連結
固態電路與系統實驗室
(R95504/ext.62400-2810)
學經歷
學歷
2002
國立交通大學電機博士
1996
國立交通大學電機碩士
1991
國立中央大學電機學士
經歷
2017/08-present
國立成功大學晶片系統研發中心 主任
2011/08-present
國立成功大學電機系教授
2011/08-2014/07
國立成功大學電機工廠主任
2009/01-2012/12
國際電機電子工程師學會 固態電路學會 台南支會主席
2008/08-2011/07
國立成功大學電機系副教授
2003/02-2008/07
國立成功大學電機系助理教授
2002/10-2003/01
工研院系統晶片中心工程師
研究領域
  • 混合信號積體電路設計、測試與可測試設計
  • 電腦輔助積體電路設計
著作
期刊論文( Journal )
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  1. Chung-Wei Hsu, Soon-Jyh Chang, Chun-Po Huang, Li-Jen Chang, Ya-Ting Shyu, Chih-Huei Hou, Hwa-An Tseng, Chih-Yuan Kung, and Huan-Jui Hu, "A 12-b 40-MS/s Calibration-Free SAR ADC," IEEE Transactions on Circuits and Systems - I, vol. 65, no. 3, pp.881-890, Mar. 2018. (SCI, EI)
  2. Yen-Long Lee, Soon-Jyh Chang, Yen-Chi Chen, and Yu-Po Cheng,"An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits",( IEEE Transactions on Circuits and Systems II: Express Briefs, May 2017)
  3. Chin-Lung Yang, Chung-Kai Chang, Shuenn-Yuh Lee, Soon-Jyh Chang, and Lih-Yih Chiou, "Efficient Four-Coil Wireless Power Transfer for Deep Brain Stimulation", IEEE Transactions on Microwave Theory and Techniques, vol. 65, no. 7, pp. 2496-2507, July 2017.
  4. I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang,and Hsin-Wen Ting, "Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017. (SCI,EI)
  5. Chun-Po Huang, Hsin-Wen Ting,and Soon-Jyh Chang, "Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs," IEEE Transactions on Instrumentation and Measurement, 2016. (SCI,EI)
  6. Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, and Soon-Jyh Chang, "A Systematic Design Methodology of Asynchronous SAR ADCs," IEEE Transactions on VLSI Systems, 2016. (SCI,EI)
  7. Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, and Soon-Jyh Chang, "An Efficient and Effective Methodology to Control Turn-on Sequence of Power Switches for Power Gating Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,DOI 10.1109/TCAD.2016.2523916, 2016. (SCI,EI)
  8. An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, and Soon-Jyh Chang, "A Capacitance-Ratio Quantification Design for Linearity Test in Differential Top-Plate Sampling SAR ADCs," International Journal of Circuit Theory and Applications, doi: 10.1002/cta.2014, 2014. (SCI, EI)
  9. Peng-Yu Chen, Guan-Ying Huang, Ya-Ting Shyu, and Soon-Jyh Chang, "A Primary-Auxiliary Temperature Sensing Scheme for Multiple Hotspots in System-on-a-Chips," IEEE Sensors Journal, vol. 14, no. 8, pp. 2633-2643, Aug. 2014. (SCI, EI)
  10. An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, and Soon-Jyh Chang, "A Low-Cost Stimulus Design for Linearity Test in SAR ADCs," IEICE Transactions on Electronics, vol. E97-C, no. 6, pp. 538-545, Jun. 2014. (SCI, EI)
  11. I-Jen Chao, Ching-Wen Hou, Bin-Da Liu, Soon-Jyh Chang, and Chun-Yueh Huang, "A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder," IEICE Transactions on Electronics, vol. E97-C, no. 6, pp. 526-537, Jun. 2014. (SCI, EI)
  12. Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin and Soon-Jyh Chang, "An Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops," IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp. 624-635, Apr. 2013. (SCI, EI)
  13. Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu and Ying-Zu Lin, "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," IEEE Transactions on VLSI Systems, vol. 21, no. 3, pp. 584-588, Mar. 2013. (SCI, EI)
  14. Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, and Soon-Jyh Chang, "A 9-bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS," IEEE Transactions on Circuits and Systems - I, vol. 60, no. 3, pp. 570-581, Mar. 2013. (SCI, EI)
  15. Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang, "Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 12, pp.1789-1802, Dec. 2012. (SCI, EI)
  16. Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, and Soon-Jyh Chang, "A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E95-A, no.12, pp.2415-2423, Dec. 2012. (SCI, EI)
  17. Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, and Ying-Zu Lin, "1-uW 10-bit 200-kS/s SAR ADC with a Bypass Window for Biomedical Applications," IEEE Journal of Solid-State Circuits, vol.47, no.11, pp.2783-2795, Nov. 2012. (SCI, EI)
  18. Ren-Li Chen and Soon-Jyh Chang, "A 6-bit Current-Steering DAC with Compound Current cells for Both Communication and Rail-to-Rail Programmable Voltage Source Applications," IEEE Transactions on Circuits and Systems - II, vol.46, no.11, pp.746-750, Nov. 2012. (SCI, EI)
  19. I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, and Hsin-Wen Ting, "A 3rd-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing," IEICE Transactions on Electronics, vol.E95-C, no.11, pp.1799-1809, Nov. 2012. (SCI, EI)
  20. Ren-Li Chen, Hsin-Wen Ting and Soon-Jyh Chang, "Six-bit 2.7-GS/s 5.4-mW Nyquist Complementary Metal-Oxide Semiconductor Digital-to-Analogue Converter for Ultra-Wideband Transceivers," IET Circuits Devices & Systems, vol. 6, iss. 2, pp. 95-102, 2012. (SCI, EI)
  21. Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting and Chih-Hao Huang, "Transition-Code Based Linearity Test Method for Pipelined ADCs with Digital Error Correction," IEEE Transactions on VLSI Systems, vol. 19, no. 12, pp.2158-2169, Dec. 2011. (SCI, EI)
  22. Hsin-Wen Ting, Soon-Jyh Chang, and Su-Ling Huang, "A Design of Linearity Built-in Self-Test for Current-Steering DAC,"Journal of Electronic Testing: Theory and Applications, vol. 27, pp.85-94, Feb. 2011. (SCI, EI)
  23. Jin-Fu Lin and Soon-Jyh Chang, "A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages," IEICE Transactions on Electronics, vol.E94-C, no.1, pp.89-101, Jan. 2011. (SCI, EI)
  24. Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guan-Ying Huang, "An Asynchronous Binary-Search ADC Architecture with a Reduced Comparator Count," IEEE Transactions on Circuits and Systems - I, vol. 57, no. 8, pp.1829-1837, Aug. 2010. (SCI, EI)
  25. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin, "A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure," IEEE Journal of Solid-State Circuits, vol.45, no.4, pp.731-740, Apr. 2010. (SCI, EI)
  26. Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu and Chih-Hao Huang, "A 10-bit 60-MS/s Low-Power Pipelined ADC with Split-Capacitor CDS Technique," IEEE Transactions on Circuits and Systems - II, vol.57, no.3, pp.163-167, Mar. 2010. (SCI, EI)
  27. Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A 5-bit 3.2-GS/s Flash ADC with a Digital Offset Calibration Scheme,"IEEE Transactions on VLSI Systems, vol.18, no.3, pp.509-513, Mar. 2010. (SCI, EI)
  28. Jin-Fu Lin, Soon-Jyh Chang, Chin-Fong Chiu, Hann-Huei Tsai and Jiann-Jong Wang, "Low-Power and Wide-Bandwidth Cyclic ADC with Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application," IEEE Sensors Journal, vol.9, no.12, pp.2044-2054, Dec. 2009. (SCI, EI)
  29. Ying-Zu Lin, Soon-Jyh Chang and Yen-Ting Liu, "A 5-bit 4.2-GS/s Flash ADC in 0.13-um CMOS Process," IEICE Transactions on Electronics, vol.E92-C no.2, pp.258-268, Feb. 2009. (SCI, EI)
  30. Soon-Jyh Chang, Ying-Zu Lin and Yen-Ting Liu, "A Digitally Calibrated CMOS Transconductor with a 100-MHz Bandwidth and 75-dB SFDR," IEEE Transactions on Circuits and Systems - II, vol.55, no.11, pp.1089-1093, Nov. 2008. (SCI, EI)
  31. Hsin-Hung Ou, Bin-Da Liu and Soon-Jyh Chang, "A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture," IEICE Transactions on Electronics, vol.E91-C, no.9, pp.1480-1487, Sep. 2008. (SCI, EI)
  32. Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Bin-Da Liu, Chien-Hung Tsai and Soon-Jyh Chang, "A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter," IEICE Transactions on Electronics, vol.E91-C, no.5, pp.809-812, May 2008. (SCI, EI)
  33. Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.2, pp.461-468, Feb. 2008. (SCI, EI)
  34. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "Histogram Based Testing Method for Estimating A/D Converter Performance," IEEE Transactions on Instrumentation & Measurement, vol.57, no.2, pp.420-427, Feb. 2008. (SCI, EI)
  35. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST," Journal of Electronic Testing: Theory and Applications, vol.23, pp.549-558, Dec. 2007.
  36. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits," Journal of Information Science and Engineering, vol.19, no.4, pp.637-651, July 2003. (SCI, EI)
  37. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Journal of Electronic Testing: Theory and Applications, vol.18, issue.2, pp.571-581, Dec. 2002. (SCI, EI)
  38. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "BIST Scheme for DAC Testing," IET Electronics Letters, vol.38, no.15, pp.776-777, July 18th, 2002. (SCI, EI)
會議論文( Conference )
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  1. C.-C. Lee, S.-J. Chang, "Modified BER Test for SAR ADCs," International Test Conference in Asia (ITC-Asia), September 2020.
  2. H.-S. Wu, S.-J. Chang, "An 11-bit 40-MS/s SAR ADC Using a Low-complexity Code-dependent Reference Ripple Suppression Technique," International Conference on Analog VLSI Circuits (AVIC), October 2019.
  3. Y.-S. Lin, S.-J. Chang, and C.-L. Wei, “A Noise-shaping SAR Assisted MASH 2-1 Sigma Delta Modulator,” Taiwan and Japan Conference on Circuits and Systems (TJCAS), August 2019.
  4. H. Hu, Y. Cheng and S. Chang, "A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
  5. Y. Cheng, H. Hu and S. Chang, "A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
  6. Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, and Jai-Ming Lin, "A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling," Proceedings of the 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 17-18, 2016. (Jan. 25-28, 2016, Macao, China)
  7. Yen-Long Lee, and Soon-Jyh Chang,"A quick jitter tolerance estimation technique for bang-bang CDRs",(ITC-ASIA, Taipei, Taiwan)
  8. Chih-Huei Hou, Soon-Jyh Chang, Hao-Sheng Wu, Huan-Jui Hu, and En-Ze Cun,"An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator", (VLSI-DAT, Hsinchu, Taiwan)
  9. Ming-Hung Chien, Yen-Long Lee, Jih-Ren Goh, and Soon-Jyh Chang,"A Low Power Duobinary Voltage Mode Transmitter ", (ISLPED, Taipei, Taiwan)
  10. Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, and Soon-Jyh Chang, "A 12-bit 40-MS/s Calibration-free SAR ADC," Proceedings of the 2017 IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-4, 2017. (May 28-31, Baltimore, MD, USA)
  11. Yen-Long Lee, and Soon-Jyh Chang, "A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique"(accept) IEEE International Symposium on Next-Generation Electronics, 2016.. (SCI,EI)
  12. Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen,and Jai-Ming Lin, "A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling," (accept)IEEE Asia and South Pacific Design Automation Conference, 2016(SCI,EI)
  13. Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, and Soon-Jyh Chang, "The Pipelined ADC with Latched-Based Ring Amplifier," (accepted by) 2016 IEEE International Symposium on Circuits and Systems. (May 23-25, 2016, Montreal, Canada)
  14. Yu-Po Cheng, Yen-Long Lee, Soon-Jyh Chang, and Ming-Hung Chien, "A 7 GB/S Half-Rate Clock and Data Recovery Circuit with Compact Control Loop," (accepted by) 2016 IEEE International Symposium on VLSI Design, Automation & Test. (April 25-27, 2016, Hsinchu, Taiwan)
  15. Chia-Hsin Lee, Chih-Huei Hou, Chun-Po Huang, Soon-Jyh Chang, Yuan-Ta Hsieh, and Ying-Zong Juang, "A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS Process," (accepted by) 2016 IEEE International Symposium on VLSI Design, Automation & Test. (April 25-27, 2016, Hsinchu, Taiwan)
  16. Chun-Po Huang, Ya-Ting Shyu, Tsung-Yu Hsieh, Chieh-Wen Cheng, Wei-Chiun Liu, Hao-Ting Jian, Ying-Wei Wang, Bin-Da Liu, Soon-Jyh Chang, Lih-Yih Chiou, Chung-Ho Chen,"The SoC design of a versatile biomedical signal processor for potentiostat," Proceedings of the 2015 IEEE International Symposium on Bioelectronics and Bioinformatics, pp.59-62, 2015. (October 14-17, 2015, Beijing, China)
  17. Wei-Hao Tsai, Che-Hsun Kuo, Soon-Jyh Chang, Li-Tse Lo, Ying-Cheng Wu, and Chun-Jen Chen, "A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems," Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, pp.2425-2428, 2015. (May 24-27, 2015, Lisbon, Portugal)
  18. Shuenn-Yuh Lee, Tzung-Min Tsai, Wei-Chih Lai, Soon-Jyh Chang, and Stony Tai, "A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system," Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, pp.101-104, 2015. (May 24-27, 2015, Lisbon, Portugal)
  19. Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, and Soon-Jyh Chang, "A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer," Proceedings of the 2015 IEEE International Symposium on VLSI Design, Automation & Test, pp.1-4, 2015. (April 27-29, 2015, Hsinchu, Taiwan)
  20. Jih-Ren Goh, Yen-Long Lee, and Soon-Jyh Chang, "A dual-edge sampling CES delay-locked loop based clock and data recovery circuits," Proceedings of the 2015 IEEE International Symposium on VLSI Design, Automation & Test, pp.1-4, 2015. (April 27-29, 2015, Hsinchu, Taiwan)
  21. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low power pipelined SAR ADC with loading-free architecture," Proceedings of the 2014 IEEE International Symposium on VLSI Design, Automation & Test, pp.1-4, 2014. (April 28-30, 2014, Hsinchu, Taiwan)
  22. Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin, "A 10b 100kS/s SAR ADC with Charge Recycling Switching Method," Proceedings of the 2014 IEEE Asian Solid-State Circuits Conference, pp. 329-332, 2013. (November 10-12, 2014, KaoHsiung, Taiwan)
  23. Tzung-Min Tsai, Hsing-Chen Lin, Shuenn-Yuh Lee, and Soon-Jyh Chang, "Heart Rate Detection Through Bone-Conduction Headset," Proceedings of the 2014 IEEE Biomedical Circuits and Systems Conference, pp. 65-68,2014. (October 22-24, 2014, Lausanne, Switzerland)
  24. Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, Che-Hsun Kuo, "A 3.9-fJ/c.-S. 0.5-V 10-Bit 100-Ks/S Low Power SAR ADC with Time-Based Fixed Window," Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, pp.2345-2348, 2014. (June 1-5, 2014, Melbourne, Australia)
  25. Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Yen-Chi Chen, Jih Ren Goh, and Chung-Ming Huang, "An Area- and Power-Efficient Half-Rate Clock and Data Recovery Circuit," Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, pp.2129-2132, 2014. (June 1-5, 2014, Melbourne, Australia)
  26. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low Power Pipelined SAR ADC with Loading-Free Architecture," Proceedings of the 2014 IEEE International Symposium on VLSI Design, Automation and Test, doi: 10.1109/VLSI-DAT.2014.6834906, 2014. (April 28-30, 2014, Hsinchu, Taiwan)
  27. Shao-Hua Wan, Che-Hsun Kuo, Soon-Jyh Chang, Guan-Ying Huang, Chung-Po Huang, Goh Jih Ren, Kai-Tzeng Chiou and Cheng-Hsun Ho, "A 10-bit 50-MS/s SAR ADC with Techniques for Relaxing the Requirement on Driving Capability of Reference Voltage Buffers," Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, pp. 293-296, 2013. (November 11-13, 2013, Singapore)
  28. Guan-Ying Huang, Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu and Chun-Po Huang, "A 10 b 200 MS/s 0.82 mW SAR ADC in 40 nm CMOS," Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, pp. 289-292, 2013. (November 11-13, 2013, Singapore)
  29. Ying-Zu Lin, Ya-Ting Shyu, Che-Hsun Kuo, Guan-Ying Huang, Chun-Cheng Liu, and Soon-Jyh Chang, "Multi-Step Switching Methods for SAR ADCs," Proceedings of the 10th International Conference on Sampling Theory and Applications, pp.552-555, 2013. (July 1-5, 2013, Bremen, Germany)
  30. I-Jen Chao, Chia-Ming Kuo, Bin-Da Liu, Chun-Yueh Huang, and Soon-Jyh Chang, "A 3rd-Order Delta-Sigma Modulator with Timing-Sharing Opamp-Sharing Technique," Proceedings of the 2013 IEEE International Symposium on Circuits & Systems, pp.2002-2005, 2013. (May 19-23, 2013, Beijing, China)
  31. Ting-Zi Chen, Soon-Jyh Chang, and Guan-Ying Huang, "A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure," Proceedings of the 2013 IEEE International Symposium on VLSI Design, Automation & Test, pp.178-181, 2013. (April 22-24, 2013, Hsinchu, Taiwan)
  32. Sheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, and Soon-Jyh Chang, "A Pipelined SAR ADC with Loading-Separating Technique in 90-nm CMOS Technology," Proceedings of the 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp.264-267, 2012. (December 2-5, 2012, Kaohsiung, Taiwan)
  33. Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, and Jin-Fu Lin, "A 1-V CDS Bandgap Reference without On-Chip Resistors," Proceedings of the 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp.160-163, 2012. (December 2-5, 2012, Kaohsiung, Taiwan)
  34. Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Ying-Zu Lin, Yen-Chi Chen, Goh Jih Ren, and Chung-Ming Huang, "A 5 Gb/s 1/4-rate Clock and Data Recovery Circuit Using Dynamic Stepwise Bang-bang Phase Detector," Proceedings of the 2012 IEEE Asian Solid-State Circuits Conference, pp.141-144. (November 12-13, 2012, Kobe, Japan)
  35. Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, and Soon-Jyh Chang, "Analytical-Based Approach for Capacitor Placement with Gradient Error Compensation and Device Correlation Enhancement in Analog Integrated Circuits,"Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, pp. 635-642. (November 5-8, 2012, San Jose, California, USA)
  36. Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang and Cheng-Wu Lin, "A Power-Efficient Sizing Methodology of SAR ADCs," Proceedings of the 2012 IEEE International Symposium on Circuits & Systems, pp.365-368. (May 20-23, 2012, Seoul, Korea)
  37. Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang and Chin-Fu Lin, "A 1-V, 44.6 ppm/oC Bandgap Reference with CDS Technique," Proceedings of the 2012 IEEE International Symposium on VLSI Design, Automation & Test, Digital Object Identifier: 10.1109/VLSI-DAT.2012.6212660. (April 23-25, 2012, Hsinchu, Taiwan)
  38. Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin and Soon-Jyh Chang, "Routability-driven Placement Algorithm for Analog Integrated Circuits," Proceedings of the 2012 ACM International Symposium on Physical Design, pp.71-78. (March 25-28, 2012, Napa, California, USA)
  39. Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, and Chun-Cheng Liu, "A 0.9-V 11-bit 25-MS/s Binary-Search SAR ADC in 90-nm CMOS," Proceedings of the 2011 IEEE Asian Solid-State Circuits Conference, pp.69-72, 2011. (November 14-16, 2011, Jeju, Korea)
  40. An-Sheng Chao, Soon-Jyh Chang and Hsin-Wen Ting, "A SAR ADC BIST for Simplified Linearity Test," Proceedings of the 2011 IEEE International SOC Conference, pp.146-149, 2011. (September 26-28, 2011, Taipei, Taiwan)
  41. Cheng-Wu Lin, Cheng-Chung Lu, Chun-Po Huang, Soon-Jyh Chang, and Jai-Ming Lin, "Routing-Aware Placement Algorithms for Modem Analog Integrated Circuits," Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, 2011. (August 7-10, 2011, Seoul, Korea)
  42. Po-Chun Hsiao, I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Chun-Yueh Huang and Soon-Jyh Chang, "A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling," Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, Paper Tp1A-2, 2011. (August 7-10, 2011, Seoul, Korea)
  43. Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang and Soon-Jyh Chang, "Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits," Proceedings of the 2011 IEEE Design Automation Conference, pp.528-533, 2011. (June 5-10, 2011, San Diego, California, USA)
  44. Tz-Jing Shau, Jin-Fu Lin, Soon-Jyh Chang and Chih-Hao Huang, "Conditional Capacitor Averaging Technique to Reduce Nonlinearity Induced by Capacitor Mismatch in 2.5-bit/stage Pipelined ADCs," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.139-142, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
  45. Chao-Fang Tsai, Wan-Jing Li, Peng-Yu Chen, Ying-Zu Lin and Soon-Jyh Chang, "On-Chip Reference Oscillators with Process, Supply Voltage and Temperature Compensation," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.108-111, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
  46. Chun-Po Huang, Ying-Zu Lin, Cheng-Wu Lin, Ya-Ting Shyu and Soon-Jyh Chang, "A Systematic Design Automation Approach for Flash ADCs," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.81-84, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
  47. Tz-Jing Shau, Jin-Fu Lin and Soon-Jyh Chang, "Wide-Bandwidth Folded SHA With Sampling Capacitor Flip-Around Technique for Pipelined ADCs," Proceedings of the 2010 International Conference on High-Speed Circuits Designs, pp.86-89, 2010. (October 28-29, 2010, Taichung, Taiwan)
  48. I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Chun-Yueh Huang, and Soon-Jyh Chang, "Behavior Model for Comparator-Based Switched-Capacitor SDM with Relaxed DEM Timing," Proceedings of the 2010 IEEE International Conference on Green Circuits and Systems, pp.495-498. EI DOI: 10.1109/ICGCS.2010.5543011. (June 21-23, 2010, Shanghai, China)
  49. Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu and Soon-Jyh Chang, "A 9-bit 150-MS/s 1.53-mW Subranged SAR ADC in 90-nm CMOS," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.243-244, 2010. (June 16-18, 2010, Honolulu, Hawaii, USA)
  50. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin and Chung-Ming Huang, "A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18um CMOS," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.241-242, 2010. (June 16-18, 2010, Honolulu, Hawaii, USA)
  51. Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang and Soon-Jyh Chang, "Performance-driven Analog Placement Considering Boundary Constraint," Proceedings of the 2010 IEEE Design Automation Conference, pp.292-297, 2010. (June 13-18, 2010, Anaheim, California, USA)
  52. Ying-Zu Lin, Yu-Chang Lien and Soon-Jyh Chang, "A 0.35-1 V 0.2-3 GS/s 4-bit Low-Power Flash ADC for A Solar-Powered Wireless Module," Proceedings of the 2010 IEEE International Symposium on VLSI Design, Automation & Test, pp.299-302, 2010. (April 26-29, 2010, Hsinchu, Taiwan)
  53. Jing-Yi Huang, Chun-Hsun Wu, Le-Ren Chang-Chien and Soon-Jyh Chang, "Oscillation-Test Technique for Buck Voltage Regulator," Proceedings of the 2010 IEEE Applied Power Electronics Conference and Exposition, pp.1043-1047, 2010. (February 21-25, 2010, Palm Springs, California, USA)
  54. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang and Chih-Hao Huang, "A 10b 100MS/s 1.13mW SAR ADC with Binary Scaled Error Compensation," in IEEE ISSCC Dig. Tech. Papers, pp.386-387, 2010. (February 7-11, 2010, San Francisco, California, USA)
  55. An-Sheng Chao and Soon-Jyh Chang, "A Jitter Characterizing BIST with Pulse-Amplifying Technique," Proceedings of the 2009 IEEE Asian Test Symposium, pp.379-384, 2009. (November 23-25, 2009, Taichung, Taiwan)
  56. Jin-Fu Lin and Soon-Jyh Chang, "A Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique," Proceedings of the 2009 IEEE Asian Test Symposium, pp.57-62, 2009. (November 23-25, 2009, Taichung, Taiwan)
  57. Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin and Soon-Jyh Chang, "A 10-Bit 12-MS/s Successive Approximation ADC with 1.2-pF Input Capacitance," Proceedings of the 2009 IEEE Asian Solid-State Circuits Conference, pp.157-160, 2009. (November 16-18, 2009, Taipei, Taiwan)
  58. Ren-Li Chen and Soon-Jyh Chang, "A 5-bit 1.35-GSPS DAC for UWB Transceivers," Proceedings of the 2009 IEEE International Conference on Ultra-Wideband, pp.175-179, 2009. (September 9-11, 2009, Vancouver, Canada)
  59. Chun-Cheng Liu, Guan-Ying Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.236-237, 2009. (June 16-18, 2009, Kyoto, Japan)
  60. Hsin-Wen Ting, I-Jen Chao, Yu-Chang Lien, Soon-Jyh Chang and Bin-Da Liu, "A Low-Cost Output Response Analyzer Circuit for ADC BIST," Proceedings of the 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, 2009, Digital Object Identifier: 10.1109/CAS-ICTD.2009.4960751. (April 28-29, 2009, Chengdu, China)
  61. Ya-Ting Shyu, Cheng-Wu Lin, Jin-Fu Lin and Soon-Jyh Chang, "A gm/ID-Based Synthesis Tool for Pipelined Analog to Digital Converters," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.299-302, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  62. Chun-Cheng Liu, Yi-Ting Huang, Guan-Ying Huang, Soon-Jyh Chang, Chung-Ming Huang and Chih-Haur Huang, "A 6-bit 220-MS/s Time-Interleaving SAR ADC in 0.18-um Digital CMOS Process," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.215-218, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  63. Yu-Chang Lien, Ying-Zu Lin and Soon-Jyh Chang, "A 6-bit 1GS/s Low-Power Flash ADC," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.211-214, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  64. Wan-Jing Li, Soon-Jyh Chang and Ying-Zu Lin, "A Current Compensated Reference Oscillator," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.130-133, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  65. Cheng-Wu Lin, Pin-Dai Sue, Ya-Ting Shyu and Soon-Jyh Chang, "A Bias-Driven Approach for Automated Design of Operational Amplifiers," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.118-121, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  66. Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guan-Ying Huang, "A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS," in IEEE ISSCC Dig. Tech. Papers, pp.80-81, 2009. (February 8-12, 2009, San Francisco, California, USA)
  67. Jin-Fu Lin, Te-Chieh Kung and Soon-Jyh Chang, "A Reduced Code Linearity Test Method for Pipelined A/D Converters," Proceedings of the 2008 IEEE Asian Test Symposium, pp.111-116, 2008. (November 24-27, 2008, Sapporo, Japan)
  68. Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A 2-GS/s 6-bit Flash ADC with Offset Calibration," Proceedings of the 2008 IEEE Asian Solid-State Circuits Conference, pp.385-388, 2008. (November 3-5, 2008, Fukuoka, Japan)
  69. Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A Power-Efficient 0.8-V, 9-bit, 20-MS/s Pipelined ADC with Opamp-Shared Loading-Free Architecture," Proceedings of the 2008 IEEE International Conference on Communications, Circuits and Systems, pp.1172-1175, 2008. (May 25-27, 2008, Xiamen, China)
  70. Hung-Yu Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture," Proceedings of the 2007 IEEE TENCON, no. ThSC-O4.1, 2007. (October 30 - November 2, 2007, Taipei, Taiwan)
  71. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A 5-bit 4.2-GS/s Flash ADC in 0.13-um CMOS Process,"Proceedings of the 2007 IEEE Custom Integrated Circuits Conference, pp.213-216, 2007. (September 16-19, 2007, San Jose, California, USA)
  72. Tung-Hsing Wu, Yi-Lin Tsai and Soon-Jyh Chang, "An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC," Proceedings of the 2007 IEEE International Symposium on VLSI Design, Automation & Test, pp.236-239, 2007. (April 25-27, 2007, Hsinchu, Taiwan)
  73. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang and Soon-Jyh Chang, "An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders," Proceedings of the 2006 IEEE Asia-Pacific Conference on Circuits and Systems, pp.255-258, 2006. (December 4-7, 2006, Singapore)
  74. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Histogram Based Testing Strategy for ADCs,"Proceedings of the 2006 IEEE Asian Test Symposium, pp.51-54, 2006. (November 20-23, 2006, Fukuoka, Japan)
  75. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A Digitally Calibrated Current-Voltage Feedback Transconductor in 0.13-um CMOS Process," Proceedings of the 2006 IEEE Asian Solid-State Circuits Conference, pp.159-162, 2006. (November 13-15, 2006, Hangzhou, China)
  76. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A 6-Bit 2-GS/s Flash Analog-to-Digital Converter in 0.18-um CMOS Process," Proceedings of the 2006 IEEE Asian Solid-State Circuits Conference, pp.351-354, 2006. (November 13-15, 2006, Hangzhou, China)
  77. Zhen-Guo Ding, Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A 12-Bit, 135-MS/s Pipelined ADC Using Open-Loop Constant Gain Amplifier with Radix-Based Calibration," Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference, pp.295-299, 2006. (July 13-14, 2006, Macau, China)
  78. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu and Soon-Jyh Chang, "An Easy Testable 2-D Transform Scheme in H.264 Advanced Video Coders," Proceedings of the 4th Regional Inter-University Postgraduate Electrical & Electronic Engineering Conference, pp.124-128, 2006. (July 13-14, 2006, Macau, China)
  79. Jin-Fu Lin and Soon-Jyh Chang, "A High Speed Pipelined Analog-to-Digital Converter Using Modified Time-Shifted Correlated Double Sampling Technique," Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp.5367-5370, 2006. (May 21-24, 2006, Island of Kos, Greece)
  80. Yen-Ting Liu, Lih-Yih Chiou and Soon-Jyh Chang, "Energy-Efficient Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop," Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp.4329-4332, 2006. (May 21-24, 2006, Island of Kos, Greece)
  81. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST," Proceedings of the 2005 IEEE Asian Solid-State Circuits Conference, pp.65-68, 2005. (November 1-3, 2005, Hsinchu, Taiwan)
  82. Ying-Zu Lin and Soon-Jyh Chang, "A CMOS Current-Voltage Feedback Transconductor with an 80-dB SFDR up to 100MHz," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.945-948, 2004. (December 6-9, 2004, Tainan, Taiwan)
  83. Chih-Haur Huang, Soon-Jyh Chang and Kuen-Jong Lee, "Design of High-Resolution Pipelined Analog-to-Digital Converters Using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.625-628, 2004. (December 6-9, 2004, Tainan, Taiwan)
  84. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "An On-Chip Concurrent High Frequency Analog and Digital Sinusoidal Signal Generator," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.173-176, 2004. (December 6-9, 2004, Tainan, Taiwan)
  85. Chih-Haur Huang, Kuen-Jong Lee and Soon-Jyh Chang, "A Low-Cost Diagnosis Methodology for Pipelined A/D Converters," Proceedings of the 2004 IEEE Asian Test Symposium, pp.296-301, 2004. (November 15-17, 2004, Kenting, Taiwan)
  86. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters," Proceedings of the 2004 IEEE Asian Test Symposium, pp.52-57, 2004. (November 15-17, 2004, Kenting, Taiwan)
  87. Kuen-Jong Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng, "A Sigma-Delta Modulation Based BIST Scheme for A/D Converters," Proceedings of the 2003 IEEE Asian Test Symposium, pp.124-127, 2003. (November 17-19, 2003, Xian, China)
  88. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits," Proceedings of the 2002 IEEE International Mixed-Signal Test Workshop, pp.109-117, 2002. (June 19-21, 2002, Montreux, Switzerland)
  89. Chee-Kian Ong, Yeong-Jar Chang, Soon-Jyh Chang, Jiun-Liang Huang, Kuo-Chan Haung, Kwang-Ting Cheng and Wen-Ching Wu, "An Enhanced BIST Scheme for ADC and Non-monotonic DAC," Proceedings of the 2002 IEEE International Mixed-Signal Test Workshop, pp.171-180, 2002. (June 19-21, 2002, Montreux, Switzerland)
  90. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Proceedings of the 2002 IEEE European Test Workshop, pp.261-266, 2002. (May 26-29, 2002, Corfu, Greece)
  91. Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang and Jwu E Chen, "A DFT for semi-DC fault diagnosis for switched-capacitor circuits," Proceedings of the 1999 IEEE European Test Workshop, pp.58-63, 1999. (May 25-28, 1999, Constance, Germany)
  92. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Functional Test Pattern Generation for CMOS Operational Amplifier," Proceedings of the 1997 IEEE VLSI Test Symposium, pp.267-272, 1997. (April 27 - May 1, 1997, Monterey, California, USA)
  93. Chia‐Hsin Lee, Chih‐Huei Hou, Chun‐Po Huang, Wei‐Hao Tsai and Soon‐Jyh Chang, "A 2.5‐bit/cycle 10‐bit 160‐MS/s SAR ADC in 90‐nm CMOS Process," Proceedings of the 26th VLSI Design/CAD Symposium. (August 4-7, 2015, Hualien, Taiwan)
  94. Yung‐Kai Huang and Soon‐Jyh Chang, "A 10‐bit low‐power 100‐kS/s SAR ADC with LSB boosted technique," Proceedings of the 26th VLSI Design/CAD Symposium. (August 4-7, 2015, Hualien, Taiwan)
  95. Sin‐Yang Lin, Chi‐Yuan Huang, Hao‐Ting Jian, Chao‐Ka Yang, Meng‐ Chun Liu, Chuan‐Yu Sun, Chien‐Hung Tsai, Lih‐Yih Chiou, Soon‐Jyh Chang, and Shuenn‐Yuh Lee, "Applied to the detection and treatment of Parkinson's disease System," Proceedings of the 26th VLSI Design/CAD Symposium. (August 4-7, 2015, Hualien, Taiwan)
  96. Yen-Chi Chen, Yen-Long Lee, Yu-Po Cheng, and Soon-Jyh Chang, "A 0.5-to-4 Gbps continuous rate clock and data recovery circuit with bi-directional frequency detection," Proceedings of the 25th VLSI Design/CAD Symposium. (August 5-8, 2014, Taichung, Taiwan)
  97. Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, and Soon-Jyh Chang, "A comparator-based OTA first-order low-distortion sigma-delta modulator with split data weighted averaging algorithm logic,"
  98. Jih-Ren Goh, Soon-Jyh Chang, and Yen-Long Lee, "A 0.5-3.0 Gb/s dual-edge sampling CES DLL-CDR," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  99. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low Power and High Resolution Pipelined SAR ADC with Loading-Free Architecture," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  100. Chao-Fang Tsai, Soon-Jyh Chang, and Ying-Zu Lin, "A 10-Bit 100-MS/s Power-Efficient Flash SAR ADC,"Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  101. Kai-Tzeng Chiou and Soon-Jyh Chang, "A Speed Enhancing Technique for High-Speed Flash ADCs," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  102. Peng-Yu Chen, Guan-Ying Huang, Soon-Jyh Chang, and Ya-Ting Shyu, "Temperature Measuring Scheme for Multiple Hotspots in System Chips," Proceedings of the 7th VLSI Test Technology Workshop, S4-2. (July 15-17, 2013, Taipei, Taiwan)
  103. Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, and Shao-Hua Wan, "A 0.5-V 10-bit 100-kS/s Asynchronous SAR ADC With Time-Based Fixed Window," Proceedings of the 23th VLSI Design/CAD Symposium. (August 7-10, 2012, Kenting, Taiwan)
  104. Ting-Zi Chen, Guan-Ying Huang, and Soon-Jyh Chang, "A 10-bit 50-MS/s Asynchronous SAR ADC with Low Input Capacitance," Proceedings of the 23th VLSI Design/CAD Symposium. (August 7-10, 2012, Kenting, Taiwan)
  105. I-Jen Chao, Wei-Chih Chen, Chia-Ming Kuo, Bin-Da Liu, Hsin-Wen Ting, Soon-Jyh Chang and Chun-Yueh Huang, "A Low-Distortion Relaxed-DEM-Timing Delta-Sigma Modulator without Extra Adder in the Quantizer Input," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 2011, Yunlin, Taiwan)
  106. Chien-Liang Kuo and Soon-Jyh Chang, "A 20-MHz On-Chip Relaxation Oscillator," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 20101, Yunlin, Taiwan)
  107. Cheng-Wu Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang and Jai-Ming Lin, "Mismatches-Aware Common-Centroid Placement for Capacitor Arrays," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 2011, Yunlin, Taiwan)
  108. An-Sheng Chao and Soon-Jyh Chang, "A SAR ADC BIST for Linearity Test Time Reduction," Proceedings of the 5th VLSI Test Technology Workshop, pp.59-63, 2011. (July 13-15, 2011, Nantou, Taiwan)
  109. Ren-Li Chen, Soon-Jyh Chang and Hsin-Wen Ting, "A Low-Cost Low-Power Current-Steering DAC for UWB Transceivers," Proceedings of the 21th VLSI Design/CAD Symposium. (August 3-6, 2010, Kaohsiung, Taiwan)
  110. Chao-Fang Tsai, Wan-Jing Li, Peng-Yu Chen, Ying-Zu Lin and Soon-Jyh Chang, "On-Chip Reference Oscillators with Process, Supply Voltage and Temperature Compensation," Proceedings of the 21th VLSI Design/CAD Symposium. (August 3-6, 2010, Kaohsiung, Taiwan)
  111. Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin and Soon-Jyh Chang, "A 10-bit Low Input Capacitance SAR ADC,"Proceedings of the 20th VLSI Design/CAD Symposium. (August 4-7, 2009, Hualien, Taiwan)
  112. Jin-Fu Lin and Soon-Jyh Chang, "An Improved Reduced Code Linearity Test Method for Pipelined A/D Converters,"Proceedings of the 3rd VLSI Test Technology Workshop. (July 15-17, 2009, Nantou, Taiwan)
  113. Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A Digitally Calibrated 5-bit 3.2-GS/s Flash ADC," Proceedings of the 19th VLSI Design/CAD Symposium. (August 5-8, 2004, Kenting, Taiwan)
  114. Jin-Fu Lin, Te-Chieh Kung and Soon-Jyh Chang, "Linearity Testing of the Pipelined ADCs Using the Characteristic Observation Method," Proceedings of the 19th VLSI Design/CAD Symposium. (August 5-8, 2004, Kenting, Taiwan)
  115. Yu-Chang Lien, Hsin-Wen Ting, I-Chun Chen, Soon-Jyh Chang and Bin-Da Liu, "A Low-Cost Sine-Wave Histogram Analyzer for ADC BIST," Proceedings of the 2nd VLSI Test Technology Workshop. (July 16-18, 2008, Tainan, Taiwan)
  116. Te-Chieh Kung, Jin-Fu Lin and Soon-Jyh Chang, "Linearity Testing of the Pipelined ADCs Using the Characteristic Observation Method," Proceedings of the 2nd VLSI Test Technology Workshop. (July 16-18, 2008, Tainan, Taiwan)
  117. Cheng-Wu Lin and Soon-Jyh Chang, "An Automated Synthesis Tool for Fully Differential OPAMPs," Proceedings of the 18th VLSI Design/CAD Symposium. (August 7-10, 2007, Hualien, Taiwan)
  118. Hung-Yu Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture," Proceedings of the 18th VLSI Design/CAD Symposium. (August 7-10, 2007, Hualien, Taiwan)
  119. An-Sheng Chao, Soon-Jyh Chang, Shih-Ming Luo, Steven Huang and Chih-Haur Huang, "Design and Implementation of a Built-in Self-Test Scheme for Phase Lock Loops," Proceedings of the 1st VLSI Test Technology Workshop. (July 26-27, 2007, Hsinchu, Taiwan)
  120. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang and Soon-Jyh Chang, "An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders," Proceedings of the 17th VLSI Design/CAD Symposium. (August 8-11, 2006, Hualien, Taiwan)
  121. Zhen-Guo Ding, Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A Self-Calibrated Pipelined ADC with Open-Loop Constant Gain Amplifier," Proceedings of the 17th VLSI Design/CAD Symposium. (August 8-11, 2006, Hualien, Taiwan)
  122. Ying-Zu Lin and Soon-Jyh Chang, "A Digitally Calibrated CMOS Current-Voltage Feedback Transconductor with an 80-dB SFDR up to 100MHz," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  123. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "A Reconfigurable Sinusoidal Signal Generator for Analog-to-Digital Converter Built-In Self-Test," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  124. Yen-Ting Liu, Lih-Yih Chiou and Soon-Jyh Chang, "Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop for Low Power System," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  125. Jin-Fu Lin and Soon-Jyh Chang, "A 1.8-V 10-Bit 100 MS/S Pipelined ADC using Modified Time-Shifted CDS Technique," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  126. Ying-Zu Lin and Soon-Jyh Chang, "A High-SFDR and Wide-Bandwidth CMOS Current-Voltage Feedback Transconductor," Proceedings of the 15th VLSI Design/CAD Symposium. (August 10-13, 2004, Kenting, Taiwan)
  127. Chih-Haur Huang, Soon-Jyh Chang and Kuen-Jong Lee, "Design of High-Resolution Pipelined Analog-to-Digital Converters using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique," Proceedings of the 15th VLSI Design/CAD Symposium. (August 10-13, 2004, Kenting, Taiwan)
  128. Kuen-Jong Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng, "A Sigma-Delta Modulation Based BIST Scheme for A/D Converters," Proceedings of the 14th VLSI Design/CAD Symposium. (August 12-15, 2003, Hualien, Taiwan)
  129. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Proceedings of the 12th VLSI Design/CAD Symposium. (August 14-17, 2001, Kuansi, Hsinchu, Taiwan)
  130. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Functional Test Pattern Generation for CMOS Operational Amplifier," Proceedings of the 7th VLSI Design/CAD Symposium, pp.65-68. (August 13-16, 1996, Shihmen Dam, Taoyuan, Taiwan)
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  10. 張順志、劉純成、黃冠穎:「具輔助預測電路之逐漸趨近式類比數位轉換器及其方法」中華民國發明專利第I454064號。(申請日:2010/12/16; 公告日:2012/07/01; 授權日:2014/09/21)
  11. 張順志、陳鵬宇、林進富:「低電壓能階參考位準電路」中華民國發明專利第I453894號。(申請日:2011/11/23; 公告日:2013/06/01; 授權日:2014/09/21)
  12. 張順志、林英儒、劉純成:「分段式類比數位轉換器及其方法」中華民國發明專利第I452846號。(申請日:2010/12/16; 公告日:2012/07/01; 授權日:2014/09/11)
  13. 張順志、鐘明良、陳柏穎、黃崇銘:「記憶體單元及相關記憶體裝置」中華民國發明專利第I446342號。(申請日:2010/06/03; 公告日:2011/12/26; 授權日:2014/7/21)
  14. 張順志、林進富:「乘法型數位至類比轉換器及方法」中華民國發明專利第I423595號。(申請日:2010/11/09; 公開日:2012/05/16; 授權日:2014/01/11)
  15. 張順志、鐘明良、陳柏穎、黃崇銘:「記憶體單元及相關記憶體裝置」中國大陸發明專利第102280137B號。(申請日:2010/06/08; 公告日:2011/12/14; 授權日:2013/07/10)
  16. Soon-Jyh Chang, Guan-Ying Huang, Chung-Ming Huang: Successive Approximation Analog to Digital Converter with A Direct Switching Technique for Capacitor Array through Comparator Output and Method Thereof, United States Patent 8477058. (Filing date: Oct. 12, 2011; Issue date: Jul. 2, 2013)
  17. Soon-Jyh Chang, Yen Long Lee, Chung-Ming Huang: Clock and Data Recovery (CDR) Architecture and Phase Detector Thereof, United States Patent 8457269. (Filing date: Oct. 27, 2011; Issue date: Jun. 4, 2013)
  18. Soon-Jyh Chang, Chun-Cheng Liu, Guan-Ying Huang: Successive Approximation Analog-to-Digital Converter Having Auxiliary Prediction Circuit and Method Thereof, United States Patent 8416116. (Filing date: Mar. 21, 2011; Issue date: Apr. 9, 2013)
  19. Soon-Jyh Chang, Guan-Ying Huang, Chun-Cheng Liu, Chung-Ming Huang, Jin-Fu Lin, Chih-Haur Huang: Successive Approximation Register ADC with A Window Predictive Function, United States Patent 8390501. (Filing date: Apr. 28, 2011; Issue date: Mar. 5, 2013)
  20. Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu: Subrange Analog-to-Digital Converter and Method Thereof, United States Patent 8310388. (Filing date: Mar. 17, 2011; Issue date: Nov. 13, 2012 )
  21. 張順志、趙安生、黃志豪、黃國展、羅世明:「抖動量測裝置及其方法」中華民國發明專利第I373621號。(申請日:2008/07/14; 公告日:2009/02/16; 授權日:2012/10/01)
  22. Soon-Jyh Chang, Ming-Liang Chung, Po-Ying Chen, Chung-Ming Huang: Memory Cell and an Associated Memory Device, United States Patent 8228705. (Filing date: Apr. 22, 2010; Issue date: Jul. 24, 2012)
  23. Soon-Jyh Chang, Jin-Fu Lin: Multiplying DAC and a Method Thereof, United States Patent 8217819. (Filing date: Nov. 8, 2010; Issue date: Jul. 10, 2012)
  24. 張順志、林進富、黃志豪:「偽差動切換電容式電路」中國大陸發明專利第CN101753104B號。(申請日:2008/12/05; 公告日:2010/06/23; 授權日:2012/05/30)
  25. 張順志、劉純成、黃志豪:「具二進制錯誤容忍機制之逐漸逼近式類比至數位轉換器」中國大陸發明專利第CN101729069B號。(申請日:2008/10/27; 公告日:2010/06/09; 授權日:2011/12/28)
  26. 張順志、趙安生、黃志豪、黃國展、羅世明:「抖動測量裝置及其方法」中國大陸發明專利CN101349717B號。 (申請日:2008/07/16; 公告日:2009/01/21; 授權日:2011/09/28)
  27. An-Sheng Chao,?Soon-Jyh Chang, Kuo-Chan Huang, Chih-Haur Huang, Shih-Ming Luo: Device for Jitter Measurement and Method Thereof, United States Patent 7957923. (Filing date: May 8, 2008; Issue date: Jun. 7, 2011)
  28. Soon-Jyh Chang, Jin-Fu Lin, Chih-Haur Huang: Stage-Resolution Scalable Opamp-Sharing Technique for Pipelined/Cyclic ADC, United States Patent 7924204. (Filing date: Oct. 7, 2008; Issue date: Apr. 12, 2011)
  29. 張順志、林進富、黃志豪:「應用於偽差動切換電容式電路之積分形式共模電壓穩定技術」中華民國發明專利第I335130號。(申請日:2008/11/14; 公告日:2010/05/16; 授權日:2010/12/21)
  30. Soon-Jyh Chang, Chun-Cheng Liu, Chih-Haur Huang: Successive Approximation ADC with Binary Error Tolerance Mechanism, United States Patent 7724174. (Filing date: Oct. 7, 2008; Issue date: May 25, 2010)
  31. Soon-Jyh Chang, Jin-Fu Lin, Chih-Haur Huang: Integrator-Based Common-Mode Stabilization Technique for Pseudo-Differential Switched-Capacitor Circuits, United States Patent 7724063. (Filing date: Dec. 2, 2008; Issue date: May 25, 2010)
  32. 張順志、劉純成、黃志豪:「具二進制錯誤容忍機制之逐漸逼近式類比之數位轉換器」中華民國發明專利第I328356號。(申請日:2008/10/03; 公告日:2010/04/16; 授權日:2010/08/01)
  33. 劉濱達、丁信文、張順志:「以直方圖為基礎之類比數位轉換器測試方法」中華民國發明專利第I311866號。(申請日:2006/03/20; 公告日:2007/10/01; 授權日:2009/07/01)
  34. 張順志、趙安生:「以晶片內建環型振盪器為基礎之互補式金氧半導體溫度感測器」中華民國發明專利第I292474號。(申請日:2006/03/28; 公告日:2007/10/01; 授權日:2008/01/11)
其他
more
less
  1. 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作—子計畫三: 應用於高安全性且低耗能物聯網系統的類比至數位轉換器之研製(1/2)
  2. 具高安全性且易於整合的車用類比至數位轉換器之研製 MOST 105-2221-E-006-240-MY3
  3. 低耗能且易於整合之逐漸逼近式類比至數位轉換器研製 MOST 104-2220-E-006-012
  4. 考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫三:應用於三維晶片之溫度感測與時脈電路設計技術研發,2013/08/01 - 2016/07/31,NSC-102-2221-E-006-263-MY3。
  5. 超低耗能類比至數位轉換器研製(2/2),2013/05/01 - 2014/04/30,NSC 102-2220-E-006 -015。
  6. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(3/3),2012/08/01 - 2013/07/31,NSC 101-2220-E-006-005。
  7. 超低耗能類比至數位轉換器研製(1/2),2012/05/01 - 2013/04/30,NSC 101-2220-E-006 -024。
  8. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(2/3),2011/08/01 - 2012/07/31,NSC 100-2220-E-006-005。
  9. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(1/3),2010/08/01 - 2011/07/31,NSC 99-2220-E-006-018。
  10. 低功率高速資料轉換器設計與自動化設計之研發,2009/08/01 - 2012/07/31,NSC 98-2221-E-006-156-MY3。
  11. 高速資料轉換器測試與設計自動化之研發,2007/08/01 - 2009/07/31,NSC 96-2221-E-006-294-MY2。
  12. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(3/3),2007/08/01 - 2008/07/31,NSC 96-2220-E-006-004。
  13. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(2/3),2006/08/01 - 2007/07/31,NSC 95-2220-E-006-009。
  14. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(3/3),2006/08/01 - 2007/07/31,NSC 95-2220-E-006-004。
  15. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(1/3),2005/08/01 - 2006/07/31,NSC 94-2220-E-006-016。
  16. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(2/3),2005/08/01 - 2006/07/31,NSC 94-2220-E-006-010。
  17. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(1/3),2004/08/01 - 2005/07/31,NSC 93-2220-E-006-010。
  18. 於系統單晶片中類比與混合訊號電路測試與可測試設計之研究,2003/09/01 - 2004/07/31,NSC 92-2218-E-006-042。
其他
more
less
  1. 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作—子計畫三: 應用於高安全性且低耗能物聯網系統的類比至數位轉換器之研製(1/2)
  2. 具高安全性且易於整合的車用類比至數位轉換器之研製 MOST 105-2221-E-006-240-MY3
  3. 低耗能且易於整合之逐漸逼近式類比至數位轉換器研製 MOST 104-2220-E-006-012
  4. 考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫三:應用於三維晶片之溫度感測與時脈電路設計技術研發,2013/08/01 - 2016/07/31,NSC-102-2221-E-006-263-MY3。
  5. 超低耗能類比至數位轉換器研製(2/2),2013/05/01 - 2014/04/30,NSC 102-2220-E-006 -015。
  6. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(3/3),2012/08/01 - 2013/07/31,NSC 101-2220-E-006-005。
  7. 超低耗能類比至數位轉換器研製(1/2),2012/05/01 - 2013/04/30,NSC 101-2220-E-006 -024。
  8. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(2/3),2011/08/01 - 2012/07/31,NSC 100-2220-E-006-005。
  9. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(1/3),2010/08/01 - 2011/07/31,NSC 99-2220-E-006-018。
  10. 低功率高速資料轉換器設計與自動化設計之研發,2009/08/01 - 2012/07/31,NSC 98-2221-E-006-156-MY3。
  11. 高速資料轉換器測試與設計自動化之研發,2007/08/01 - 2009/07/31,NSC 96-2221-E-006-294-MY2。
  12. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(3/3),2007/08/01 - 2008/07/31,NSC 96-2220-E-006-004。
  13. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(2/3),2006/08/01 - 2007/07/31,NSC 95-2220-E-006-009。
  14. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(3/3),2006/08/01 - 2007/07/31,NSC 95-2220-E-006-004。
  15. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(1/3),2005/08/01 - 2006/07/31,NSC 94-2220-E-006-016。
  16. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(2/3),2005/08/01 - 2006/07/31,NSC 94-2220-E-006-010。
  17. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(1/3),2004/08/01 - 2005/07/31,NSC 93-2220-E-006-010。
  18. 於系統單晶片中類比與混合訊號電路測試與可測試設計之研究,2003/09/01 - 2004/07/31,NSC 92-2218-E-006-042。
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研究計劃
  1. 具高安全性且低耗能之物聯網晶片電路及系統之分析、設計及實作—子計畫三: 應用於高安全性且低耗能物聯網系統的類比至數位轉換器之研製(1/2)
  2. 具高安全性且易於整合的車用類比至數位轉換器之研製 MOST 105-2221-E-006-240-MY3
  3. 低耗能且易於整合之逐漸逼近式類比至數位轉換器研製 2015/05/01-2016/05/31,MOST 104-2220-E-006-012
  4. 考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法-子計畫三:應用於三維晶片之溫度感測與時脈電路設計技術研發,2013/08/01 - 2016/07/31,NSC-102-2221-E-006-263-MY3。
  5. 超低耗能類比至數位轉換器研製(2/2),2013/05/01 - 2014/04/30,NSC 102-2220-E-006 -015。
  6. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(3/3),2012/08/01 - 2013/07/31,NSC 101-2220-E-006-005。
  7. 超低耗能類比至數位轉換器研製(1/2),2012/05/01 - 2013/04/30,NSC 101-2220-E-006 -024。
  8. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(2/3),2011/08/01 - 2012/07/31,NSC 100-2220-E-006-005。
  9. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級-子計畫四:應用於低功率多核心系統之感測與時脈電路設計與自我測試技術研發(1/3),2010/08/01 - 2011/07/31,NSC 99-2220-E-006-018。
  10. 低功率高速資料轉換器設計與自動化設計之研發,2009/08/01 - 2012/07/31,NSC 98-2221-E-006-156-MY3。
  11. 高速資料轉換器測試與設計自動化之研發,2007/08/01 - 2009/07/31,NSC 96-2221-E-006-294-MY2。
  12. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(3/3),2007/08/01 - 2008/07/31,NSC 96-2220-E-006-004。
  13. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(2/3),2006/08/01 - 2007/07/31,NSC 95-2220-E-006-009。
  14. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(3/3),2006/08/01 - 2007/07/31,NSC 95-2220-E-006-004。
  15. 可攜式低功率之視訊單晶片系統研發與應用-子計畫四:可攜式低功率之視訊單晶片系統測試與可測試設計研發(1/3),2005/08/01 - 2006/07/31,NSC 94-2220-E-006-016。
  16. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(2/3),2005/08/01 - 2006/07/31,NSC 94-2220-E-006-010。
  17. 晶片系統測試平台之設計與自動化-子計畫三:SOC中類比與混合訊號電路之測試及其介面設計(1/3),2004/08/01 - 2005/07/31,NSC 93-2220-E-006-010。
  18. 於系統單晶片中類比與混合訊號電路測試與可測試設計之研究,2003/09/01 - 2004/07/31,NSC 92-2218-E-006-042。
開授課程
109學年上
指導學生
本學年度 實驗室成員
碩士班
陳盈秀
何偉立
邱薪育
許哲維
林保慶
傅俊輝
徐明琰
錢信達
盛祖丞
蔣孟儒
王奕琥
已畢業學生
碩士班
109
黃聖文   馬兆賢   林柏翰   陳奕穎   翁睿佟
108
林育賢   吳皓昇   李嘉銓   鄭乙申   謝曜聰   胡家瑋   曾華安   張力仁   羅文佳    寸恩澤   胡桓睿
107
蔡宗閔   孔致遠    簡豪廷
106
簡銘宏
105
陳文澤   侯智輝   許中瑋   李佳欣
104
鄭宇柏   黃詠愷   蔡偉浩
103
郭哲勳   徐瑱逢   吳繼仁   陳彥錡   吳佳璋
102
江凱祥   邱凱增
101
何政勳   陳家煌   萬少華   林聖雄   陳亭諮   謝坤諺
100
郭建良   王南元   謝明學   褚嶸興   陳建榮   蔡肇芳
99
陳柏穎   楊孟法   黃詩雄
98
鍾明良   邵姿菁
97
黃素鈴   莊豐任   李婉菁   孔德潔   蘇品岱   呂政家   許雅婷   連昱彰   黃意婷
96
黃宏裕   黃冠穎   羅世明   陳基清   陳卓凡
95
丁振國   劉彥廷   林城伍
94
林英儒   林進富   陳仁禮   趙安生   鄭乃禎
93
丁信文
博士班
106
李彥龍   許雅婷
105
黃俊博
103
趙安生   陳鵬宇
102
林城伍   陳仁禮   黃冠穎
99
劉純成   林進富   林英儒
98
丁信文   歐信宏
特殊榮譽
  1. 2016: 104學年度教學優良教師
  2. 2013: 102年度智慧電子國家型科技計劃「績優計畫獎」,計畫主持人:李昆忠教授(總主持人)、陳中和教授、蔡建泓教授、邱瀝毅教授、張順志教授、林家民教授、郭致宏教授
  3. 2012: 國科會101年度補助大專校院獎勵特殊優秀人才獎助
  4. 2010: IEEE Tainan Section 2010 Best GOLD Member Award
  5. 2007: 96年度國科會整合型計劃「績優計畫獎」,計畫主持人:李昆忠教授(總主持人)、陳中和教授、謝明得教授、張順志教授