NCKUEE Faculty Data
Chinese Version
Professor Soon-Jyh Chang
Address
ChiMei Building 5F R95507
Email
TEL
+886-6-2757575 ext.62380
Lab Weblink
Background
Educations
2002
Ph.D., Institute of Electronics, National Chiao-Tung University, Taiwan
1996
M.S., Institute of Electronics, National Chiao-Tung University, Taiwan
1991
B.S., Department of Electrical Engineering, National Central University, Taiwan
Experiences
2017/08-present
Director, SoC Research Center, National Cheng Kung University, Taiwan.
2011/08-present
Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan.
2011/08-2014/07
Director, Electrical Laboratories, National Cheng Kung University, Taiwan.
2009/01-2012/12
Chair, IEEE Solid-State Circuits Society Tainan Chapter.
2008/08-2011/07
Associate Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan.
2003/02-2008/07
Assistant Professor, Department of Electrical Engineering, National Cheng Kung University, Taiwan.
2002/10-2003/01
Engineer, SoC Technology Center, Industrial Technology and Research Institute (ITRI), Taiwan.
Specialities
  • Mixed-Signal Integrated Circuits Design, Test and Design-for-Testability
  • Computer Aided Integrated Circuits Design
Publication
Journal
more
less
  1. Yen-Long Lee, Soon-Jyh Chang, Yen-Chi Chen, and Yu-Po Cheng,"An Unbounded Frequency Detection Mechanism for Continuous-Rate CDR Circuits",( IEEE Transactions on Circuits and Systems II: Express Briefs, May 2017)
  2. Chin-Lung Yang, Chung-Kai Chang, Shuenn-Yuh Lee, Soon-Jyh Chang, and Lih-Yih Chiou, "Efficient Four-Coil Wireless Power Transfer for Deep Brain Stimulation", (IEEE Transactions on Microwave Theory and Techniques, July 2017)
  3. I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang,and Hsin-Wen Ting, "Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing," (accept) IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2017(SCI,EI)
  4. Chun-Po Huang, Hsin-Wen Ting,and Soon-Jyh Chang, "Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs,"(accept) IEEE Transactions on Instrumentation and Measurement, 2016(SCI,EI)
  5. Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, and Soon-Jyh Chang, "A Systematic Design Methodology of Asynchronous SAR ADCs," (accept) IEEE Transactions on VLSI Systems, 2016.(SCI,EI)
  6. Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, and Soon-Jyh Chang, "An Efficient and Effective Methodology to Control Turn-on Sequence of Power Switches for Power Gating Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,DOI 10.1109/TCAD.2016.2523916,2016(SCI,EI)
  7. An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, and Soon-Jyh Chang, "A Capacitance-Ratio Quantification Design for Linearity Test in Differential Top-Plate Sampling SAR ADCs," International Journal of Circuit Theory and Applications, doi: 10.1002/cta.2014, 2014. (SCI, EI)
  8. Peng-Yu Chen, Guan-Ying Huang, Ya-Ting Shyu, and Soon-Jyh Chang, "A Primary-Auxiliary Temperature Sensing Scheme for Multiple Hotspots in System-on-a-Chips," IEEE Sensors Journal, vol.14, no.8, pp.2633-2643, Aug. 2014. (SCI, EI)
  9. An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, and Soon-Jyh Chang, "A Low-Cost Stimulus Design for Linearity Test in SAR ADCs," IEICE Transactions on Electronics, vol.E97-C, no.6, pp.538-545, Jun. 2014. (SCI, EI)
  10. I-Jen Chao, Ching-Wen Hou, Bin-Da Liu, Soon-Jyh Chang, and Chun-Yueh Huang, "A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder," IEICE Transactions on Electronics, vol.E97-C, no.6, pp.526-537, Jun. 2014. (SCI, EI)
  11. Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin and Soon-Jyh Chang, "An Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops," IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp.624-635, Apr. 2013. (SCI, EI)
  12. Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu and Ying-Zu Lin, "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," IEEE Transactions on VLSI Systems, vol. 21, no. 3, pp.584-588, Mar. 2013. (SCI, EI)
  13. Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, and Soon-Jyh Chang, "A 9-bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS," IEEE Transactions on Circuits and Systems - I, vol. 60, no. 3, pp.570-581, Mar. 2013. (SCI, EI)
  14. Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang, "Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 12, pp.1789-1802, Dec. 2012. (SCI, EI)
  15. Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, and Soon-Jyh Chang, "A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E95-A, no.12, pp.2415-2423, Dec. 2012. (SCI, EI)
  16. Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, and Ying-Zu Lin, "1-uW 10-bit 200-kS/s SAR ADC with a Bypass Window for Biomedical Applications," IEEE Journal of Solid-State Circuits, vol.47, no.11, pp.2783-2795, Nov. 2012. (SCI, EI)
  17. Ren-Li Chen and Soon-Jyh Chang, "A 6-bit Current-Steering DAC with Compound Current cells for Both Communication and Rail-to-Rail Programmable Voltage Source Applications," IEEE Transactions on Circuits and Systems - II, vol.46, no.11, pp.746-750, Nov. 2012. (SCI, EI)
  18. I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, and Hsin-Wen Ting, "A 3rd-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing," IEICE Transactions on Electronics, vol.E95-C, no.11, pp.1799-1809, Nov. 2012. (SCI, EI)
  19. Ren-Li Chen, Hsin-Wen Ting and Soon-Jyh Chang, "Six-bit 2.7-GS/s 5.4-mW Nyquist Complementary Metal-Oxide Semiconductor Digital-to-Analogue Converter for Ultra-Wideband Transceivers," IET Circuits Devices & Systems, vol. 6, iss. 2, pp. 95-102, 2012. (SCI, EI)
  20. Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting and Chih-Hao Huang, "Transition-Code Based Linearity Test Method for Pipelined ADCs with Digital Error Correction," IEEE Transactions on VLSI Systems, vol. 19, no. 12, pp.2158-2169, Dec. 2011. (SCI, EI)
  21. Hsin-Wen Ting, Soon-Jyh Chang, and Su-Ling Huang, "A Design of Linearity Built-in Self-Test for Current-Steering DAC,"Journal of Electronic Testing: Theory and Applications, vol. 27, pp.85-94, Feb. 2011. (SCI, EI)
  22. Jin-Fu Lin and Soon-Jyh Chang, "A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages," IEICE Transactions on Electronics, vol.E94-C, no.1, pp.89-101, Jan. 2011. (SCI, EI)
  23. Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guan-Ying Huang, "An Asynchronous Binary-Search ADC Architecture with a Reduced Comparator Count," IEEE Transactions on Circuits and Systems - I, vol. 57, no. 8, pp.1829-1837, Aug. 2010. (SCI, EI)
  24. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin, "A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure," IEEE Journal of Solid-State Circuits, vol.45, no.4, pp.731-740, Apr. 2010. (SCI, EI)
  25. Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu and Chih-Hao Huang, "A 10-bit 60-MS/s Low-Power Pipelined ADC with Split-Capacitor CDS Technique," IEEE Transactions on Circuits and Systems - II, vol.57, no.3, pp.163-167, Mar. 2010. (SCI, EI)
  26. Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A 5-bit 3.2-GS/s Flash ADC with a Digital Offset Calibration Scheme,"IEEE Transactions on VLSI Systems, vol.18, no.3, pp.509-513, Mar. 2010. (SCI, EI)
  27. Jin-Fu Lin, Soon-Jyh Chang, Chin-Fong Chiu, Hann-Huei Tsai and Jiann-Jong Wang, "Low-Power and Wide-Bandwidth Cyclic ADC with Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application," IEEE Sensors Journal, vol.9, no.12, pp.2044-2054, Dec. 2009. (SCI, EI)
  28. Ying-Zu Lin, Soon-Jyh Chang and Yen-Ting Liu, "A 5-bit 4.2-GS/s Flash ADC in 0.13-um CMOS Process," IEICE Transactions on Electronics, vol.E92-C no.2, pp.258-268, Feb. 2009. (SCI, EI)
  29. Soon-Jyh Chang, Ying-Zu Lin and Yen-Ting Liu, "A Digitally Calibrated CMOS Transconductor with a 100-MHz Bandwidth and 75-dB SFDR," IEEE Transactions on Circuits and Systems - II, vol.55, no.11, pp.1089-1093, Nov. 2008. (SCI, EI)
  30. Hsin-Hung Ou, Bin-Da Liu and Soon-Jyh Chang, "A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture," IEICE Transactions on Electronics, vol.E91-C, no.9, pp.1480-1487, Sep. 2008. (SCI, EI)
  31. Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Bin-Da Liu, Chien-Hung Tsai and Soon-Jyh Chang, "A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter," IEICE Transactions on Electronics, vol.E91-C, no.5, pp.809-812, May 2008. (SCI, EI)
  32. Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.2, pp.461-468, Feb. 2008. (SCI, EI)
  33. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "Histogram Based Testing Method for Estimating A/D Converter Performance," IEEE Transactions on Instrumentation & Measurement, vol.57, no.2, pp.420-427, Feb. 2008. (SCI, EI)
  34. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST," Journal of Electronic Testing: Theory and Applications, vol.23, pp.549-558, Dec. 2007.
  35. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits," Journal of Information Science and Engineering, vol.19, no.4, pp.637-651, July 2003. (SCI, EI)
  36. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Journal of Electronic Testing: Theory and Applications, vol.18, issue.2, pp.571-581, Dec. 2002. (SCI, EI)
  37. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "BIST Scheme for DAC Testing," IET Electronics Letters, vol.38, no.15, pp.776-777, July 18th, 2002. (SCI, EI)
Conference
more
less
  1. C. -W. Hsu and S. -J. Chang, "A 1.6-GS/s 8b Flash-SAR Time-Interleaved ADC with Top-Plate Residue Based Gain Calibration," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), 2021.
  2. C.-C. Lee, S.-J. Chang, "Modified BER Test for SAR ADCs," International Test Conference in Asia (ITC-Asia), September 2020.
  3. H.-S. Wu, S.-J. Chang, "An 11-bit 40-MS/s SAR ADC Using a Low-complexity Code-dependent Reference Ripple Suppression Technique," International Conference on Analog VLSI Circuits (AVIC), October 2019.
  4. Y.-S. Lin, S.-J. Chang, and C.-L. Wei, “A Noise-shaping SAR Assisted MASH 2-1 Sigma Delta Modulator,” Taiwan and Japan Conference on Circuits and Systems (TJCAS), August 2019.
  5. H. Hu, Y. Cheng and S. Chang, "A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
  6. Y. Cheng, H. Hu and S. Chang, "A 2-GS/s 8b Flash-SAR Time-Interleaved ADC with Background Offset Calibration," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
  7. Yen-Long Lee, and Soon-Jyh Chang,"A quick jitter tolerance estimation technique for bang-bang CDRs",(ITC-ASIA, Taipei, Taiwan)
  8. Chih-Huei Hou, Soon-Jyh Chang, Hao-Sheng Wu, Huan-Jui Hu, and En-Ze Cun,"An 8-bit 400-MS/s calibration-free SAR ADC with a pre-amplifier-only comparator", (VLSI-DAT, Hsinchu, Taiwan)
  9. Ming-Hung Chien, Yen-Long Lee, Jih-Ren Goh, and Soon-Jyh Chang,"A Low Power Duobinary Voltage Mode Transmitter ", (ISLPED, Taipei, Taiwan)
  10. Chung-Wei Hsu, Li-Jen Chang, Chun-Po Huang, and Soon-Jyh Chang,"A 12-bit 40-MS/s Calibration-free SAR ADC",2017(ISCAS, Baltimore, MD, USA)
  11. Yen-Long Lee, and Soon-Jyh Chang, "A 10-fJ/bit/dB half-rate equalizer with charge-average switched-capacitor summation technique"(accept) IEEE International Symposium on Next-Generation Electronics, 2016(SCI,EI)
  12. Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen,and Jai-Ming Lin, "A testable and debuggable dual-core system with thermal-aware dynamic voltage and frequency scaling," (accept)IEEE Asia and South Pacific Design Automation Conference, 2016(SCI,EI)
  13. Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, and Soon-Jyh Chang, "The Pipelined ADC with Latched-Based Ring Amplifier," (accepted by) 2016 IEEE International Symposium on Circuits and Systems. (May 23-25, 2016, Montreal, Canada)
  14. Yu-Po Cheng, Yen-Long Lee, Soon-Jyh Chang, and Ming-Hung Chien, "A 7 GB/S Half-Rate Clock and Data Recovery Circuit with Compact Control Loop," (accepted by) 2016 IEEE International Symposium on VLSI Design, Automation & Test. (April 25-27, 2016, Hsinchu, Taiwan)
  15. Chia-Hsin Lee, Chih-Huei Hou, Chun-Po Huang, Soon-Jyh Chang, Yuan-Ta Hsieh, and Ying-Zong Juang, "A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS Process," (accepted by) 2016 IEEE International Symposium on VLSI Design, Automation & Test. (April 25-27, 2016, Hsinchu, Taiwan)
  16. Chun-Po Huang, Ya-Ting Shyu, Tsung-Yu Hsieh, Chieh-Wen Cheng, Wei-Chiun Liu, Hao-Ting Jian, Ying-Wei Wang, Bin-Da Liu, Soon-Jyh Chang, Lih-Yih Chiou, Chung-Ho Chen,"The SoC design of a versatile biomedical signal processor for potentiostat," Proceedings of the 2015 IEEE International Symposium on Bioelectronics and Bioinformatics, pp.59-62, 2015. (October 14-17, 2015, Beijing, China)
  17. Wei-Hao Tsai, Che-Hsun Kuo, Soon-Jyh Chang, Li-Tse Lo, Ying-Cheng Wu, and Chun-Jen Chen, "A 10-bit 50-MS/s SAR ADC for dual-voltage domain portable systems," Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, pp.2425-2428, 2015. (May 24-27, 2015, Lisbon, Portugal)
  18. Shuenn-Yuh Lee, Tzung-Min Tsai, Wei-Chih Lai, Soon-Jyh Chang, and Stony Tai, "A 925 MHz 1.4μW wireless energy-harvesting circuit with error-correction ASK demodulation for RFID healthcare system," Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, pp.101-104, 2015. (May 24-27, 2015, Lisbon, Portugal)
  19. Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, and Soon-Jyh Chang, "A first-order low distortion sigma-delta modulator using split DWA technique and SAR quantizer," Proceedings of the 2015 IEEE International Symposium on VLSI Design, Automation & Test, pp.1-4, 2015. (April 27-29, 2015, Hsinchu, Taiwan)
  20. Jih-Ren Goh, Yen-Long Lee, and Soon-Jyh Chang, "A dual-edge sampling CES delay-locked loop based clock and data recovery circuits," Proceedings of the 2015 IEEE International Symposium on VLSI Design, Automation & Test, pp.1-4, 2015. (April 27-29, 2015, Hsinchu, Taiwan)
  21. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low power pipelined SAR ADC with loading-free architecture," Proceedings of the 2014 IEEE International Symposium on VLSI Design, Automation & Test, pp.1-4, 2014. (April 28-30, 2014, Hsinchu, Taiwan)
  22. Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin, "A 10b 100kS/s SAR ADC with Charge Recycling Switching Method," Proceedings of the 2014 IEEE Asian Solid-State Circuits Conference, pp. 329-332, 2013. (November 10-12, 2014, KaoHsiung, Taiwan)
  23. Tzung-Min Tsai, Hsing-Chen Lin, Shuenn-Yuh Lee, and Soon-Jyh Chang, "Heart Rate Detection Through Bone-Conduction Headset," Proceedings of the 2014 IEEE Biomedical Circuits and Systems Conference, pp. 65-68,2014. (October 22-24, 2014, Lausanne, Switzerland)
  24. Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, Che-Hsun Kuo, "A 3.9-fJ/c.-S. 0.5-V 10-Bit 100-Ks/S Low Power SAR ADC with Time-Based Fixed Window," Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, pp.2345-2348, 2014. (June 1-5, 2014, Melbourne, Australia)
  25. Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Yen-Chi Chen, Jih Ren Goh, and Chung-Ming Huang, "An Area- and Power-Efficient Half-Rate Clock and Data Recovery Circuit," Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, pp.2129-2132, 2014. (June 1-5, 2014, Melbourne, Australia)
  26. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low Power Pipelined SAR ADC with Loading-Free Architecture," Proceedings of the 2014 IEEE International Symposium on VLSI Design, Automation and Test, doi: 10.1109/VLSI-DAT.2014.6834906, 2014. (April 28-30, 2014, Hsinchu, Taiwan)
  27. Shao-Hua Wan, Che-Hsun Kuo, Soon-Jyh Chang, Guan-Ying Huang, Chung-Po Huang, Goh Jih Ren, Kai-Tzeng Chiou and Cheng-Hsun Ho, "A 10-bit 50-MS/s SAR ADC with Techniques for Relaxing the Requirement on Driving Capability of Reference Voltage Buffers," Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, pp. 293-296, 2013. (November 11-13, 2013, Singapore)
  28. Guan-Ying Huang, Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu and Chun-Po Huang, "A 10 b 200 MS/s 0.82 mW SAR ADC in 40 nm CMOS," Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, pp. 289-292, 2013. (November 11-13, 2013, Singapore)
  29. Ying-Zu Lin, Ya-Ting Shyu, Che-Hsun Kuo, Guan-Ying Huang, Chun-Cheng Liu, and Soon-Jyh Chang, "Multi-Step Switching Methods for SAR ADCs," Proceedings of the 10th International Conference on Sampling Theory and Applications, pp.552-555, 2013. (July 1-5, 2013, Bremen, Germany)
  30. I-Jen Chao, Chia-Ming Kuo, Bin-Da Liu, Chun-Yueh Huang, and Soon-Jyh Chang, "A 3rd-Order Delta-Sigma Modulator with Timing-Sharing Opamp-Sharing Technique," Proceedings of the 2013 IEEE International Symposium on Circuits & Systems, pp.2002-2005, 2013. (May 19-23, 2013, Beijing, China)
  31. Ting-Zi Chen, Soon-Jyh Chang, and Guan-Ying Huang, "A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure," Proceedings of the 2013 IEEE International Symposium on VLSI Design, Automation & Test, pp.178-181, 2013. (April 22-24, 2013, Hsinchu, Taiwan)
  32. Sheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, and Soon-Jyh Chang, "A Pipelined SAR ADC with Loading-Separating Technique in 90-nm CMOS Technology," Proceedings of the 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp.264-267, 2012. (December 2-5, 2012, Kaohsiung, Taiwan)
  33. Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, and Jin-Fu Lin, "A 1-V CDS Bandgap Reference without On-Chip Resistors," Proceedings of the 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp.160-163, 2012. (December 2-5, 2012, Kaohsiung, Taiwan)
  34. Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Ying-Zu Lin, Yen-Chi Chen, Goh Jih Ren, and Chung-Ming Huang, "A 5 Gb/s 1/4-rate Clock and Data Recovery Circuit Using Dynamic Stepwise Bang-bang Phase Detector," Proceedings of the 2012 IEEE Asian Solid-State Circuits Conference, pp.141-144. (November 12-13, 2012, Kobe, Japan)
  35. Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, and Soon-Jyh Chang, "Analytical-Based Approach for Capacitor Placement with Gradient Error Compensation and Device Correlation Enhancement in Analog Integrated Circuits,"Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, pp. 635-642. (November 5-8, 2012, San Jose, California, USA)
  36. Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang and Cheng-Wu Lin, "A Power-Efficient Sizing Methodology of SAR ADCs," Proceedings of the 2012 IEEE International Symposium on Circuits & Systems, pp.365-368. (May 20-23, 2012, Seoul, Korea)
  37. Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang and Chin-Fu Lin, "A 1-V, 44.6 ppm/oC Bandgap Reference with CDS Technique," Proceedings of the 2012 IEEE International Symposium on VLSI Design, Automation & Test, Digital Object Identifier: 10.1109/VLSI-DAT.2012.6212660. (April 23-25, 2012, Hsinchu, Taiwan)
  38. Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin and Soon-Jyh Chang, "Routability-driven Placement Algorithm for Analog Integrated Circuits," Proceedings of the 2012 ACM International Symposium on Physical Design, pp.71-78. (March 25-28, 2012, Napa, California, USA)
  39. Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, and Chun-Cheng Liu, "A 0.9-V 11-bit 25-MS/s Binary-Search SAR ADC in 90-nm CMOS," Proceedings of the 2011 IEEE Asian Solid-State Circuits Conference, pp.69-72, 2011. (November 14-16, 2011, Jeju, Korea)
  40. An-Sheng Chao, Soon-Jyh Chang and Hsin-Wen Ting, "A SAR ADC BIST for Simplified Linearity Test," Proceedings of the 2011 IEEE International SOC Conference, pp.146-149, 2011. (September 26-28, 2011, Taipei, Taiwan)
  41. Cheng-Wu Lin, Cheng-Chung Lu, Chun-Po Huang, Soon-Jyh Chang, and Jai-Ming Lin, "Routing-Aware Placement Algorithms for Modem Analog Integrated Circuits," Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, 2011. (August 7-10, 2011, Seoul, Korea)
  42. Po-Chun Hsiao, I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Chun-Yueh Huang and Soon-Jyh Chang, "A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling," Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, Paper Tp1A-2, 2011. (August 7-10, 2011, Seoul, Korea)
  43. Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang and Soon-Jyh Chang, "Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits," Proceedings of the 2011 IEEE Design Automation Conference, pp.528-533, 2011. (June 5-10, 2011, San Diego, California, USA)
  44. Tz-Jing Shau, Jin-Fu Lin, Soon-Jyh Chang and Chih-Hao Huang, "Conditional Capacitor Averaging Technique to Reduce Nonlinearity Induced by Capacitor Mismatch in 2.5-bit/stage Pipelined ADCs," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.139-142, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
  45. Chao-Fang Tsai, Wan-Jing Li, Peng-Yu Chen, Ying-Zu Lin and Soon-Jyh Chang, "On-Chip Reference Oscillators with Process, Supply Voltage and Temperature Compensation," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.108-111, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
  46. Chun-Po Huang, Ying-Zu Lin, Cheng-Wu Lin, Ya-Ting Shyu and Soon-Jyh Chang, "A Systematic Design Automation Approach for Flash ADCs," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.81-84, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
  47. Tz-Jing Shau, Jin-Fu Lin and Soon-Jyh Chang, "Wide-Bandwidth Folded SHA With Sampling Capacitor Flip-Around Technique for Pipelined ADCs," Proceedings of the 2010 International Conference on High-Speed Circuits Designs, pp.86-89, 2010. (October 28-29, 2010, Taichung, Taiwan)
  48. I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Chun-Yueh Huang, and Soon-Jyh Chang, "Behavior Model for Comparator-Based Switched-Capacitor SDM with Relaxed DEM Timing," Proceedings of the 2010 IEEE International Conference on Green Circuits and Systems, pp.495-498. EI DOI: 10.1109/ICGCS.2010.5543011. (June 21-23, 2010, Shanghai, China)
  49. Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu and Soon-Jyh Chang, "A 9-bit 150-MS/s 1.53-mW Subranged SAR ADC in 90-nm CMOS," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.243-244, 2010. (June 16-18, 2010, Honolulu, Hawaii, USA)
  50. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin and Chung-Ming Huang, "A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18um CMOS," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.241-242, 2010. (June 16-18, 2010, Honolulu, Hawaii, USA)
  51. Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang and Soon-Jyh Chang, "Performance-driven Analog Placement Considering Boundary Constraint," Proceedings of the 2010 IEEE Design Automation Conference, pp.292-297, 2010. (June 13-18, 2010, Anaheim, California, USA)
  52. Ying-Zu Lin, Yu-Chang Lien and Soon-Jyh Chang, "A 0.35-1 V 0.2-3 GS/s 4-bit Low-Power Flash ADC for A Solar-Powered Wireless Module," Proceedings of the 2010 IEEE International Symposium on VLSI Design, Automation & Test, pp.299-302, 2010. (April 26-29, 2010, Hsinchu, Taiwan)
  53. Jing-Yi Huang, Chun-Hsun Wu, Le-Ren Chang-Chien and Soon-Jyh Chang, "Oscillation-Test Technique for Buck Voltage Regulator," Proceedings of the 2010 IEEE Applied Power Electronics Conference and Exposition, pp.1043-1047, 2010. (February 21-25, 2010, Palm Springs, California, USA)
  54. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang and Chih-Hao Huang, "A 10b 100MS/s 1.13mW SAR ADC with Binary Scaled Error Compensation," in IEEE ISSCC Dig. Tech. Papers, pp.386-387, 2010. (February 7-11, 2010, San Francisco, California, USA)
  55. An-Sheng Chao and Soon-Jyh Chang, "A Jitter Characterizing BIST with Pulse-Amplifying Technique," Proceedings of the 2009 IEEE Asian Test Symposium, pp.379-384, 2009. (November 23-25, 2009, Taichung, Taiwan)
  56. Jin-Fu Lin and Soon-Jyh Chang, "A Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique," Proceedings of the 2009 IEEE Asian Test Symposium, pp.57-62, 2009. (November 23-25, 2009, Taichung, Taiwan)
  57. Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin and Soon-Jyh Chang, "A 10-Bit 12-MS/s Successive Approximation ADC with 1.2-pF Input Capacitance," Proceedings of the 2009 IEEE Asian Solid-State Circuits Conference, pp.157-160, 2009. (November 16-18, 2009, Taipei, Taiwan)
  58. Ren-Li Chen and Soon-Jyh Chang, "A 5-bit 1.35-GSPS DAC for UWB Transceivers," Proceedings of the 2009 IEEE International Conference on Ultra-Wideband, pp.175-179, 2009. (September 9-11, 2009, Vancouver, Canada)
  59. Chun-Cheng Liu, Guan-Ying Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.236-237, 2009. (June 16-18, 2009, Kyoto, Japan)
  60. Hsin-Wen Ting, I-Jen Chao, Yu-Chang Lien, Soon-Jyh Chang and Bin-Da Liu, "A Low-Cost Output Response Analyzer Circuit for ADC BIST," Proceedings of the 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, 2009, Digital Object Identifier: 10.1109/CAS-ICTD.2009.4960751. (April 28-29, 2009, Chengdu, China)
  61. Ya-Ting Shyu, Cheng-Wu Lin, Jin-Fu Lin and Soon-Jyh Chang, "A gm/ID-Based Synthesis Tool for Pipelined Analog to Digital Converters," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.299-302, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  62. Chun-Cheng Liu, Yi-Ting Huang, Guan-Ying Huang, Soon-Jyh Chang, Chung-Ming Huang and Chih-Haur Huang, "A 6-bit 220-MS/s Time-Interleaving SAR ADC in 0.18-um Digital CMOS Process," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.215-218, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  63. Yu-Chang Lien, Ying-Zu Lin and Soon-Jyh Chang, "A 6-bit 1GS/s Low-Power Flash ADC," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.211-214, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  64. Wan-Jing Li, Soon-Jyh Chang and Ying-Zu Lin, "A Current Compensated Reference Oscillator," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.130-133, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  65. Cheng-Wu Lin, Pin-Dai Sue, Ya-Ting Shyu and Soon-Jyh Chang, "A Bias-Driven Approach for Automated Design of Operational Amplifiers," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp.118-121, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
  66. Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guan-Ying Huang, "A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS," in IEEE ISSCC Dig. Tech. Papers, pp.80-81, 2009. (February 8-12, 2009, San Francisco, California, USA)
  67. Jin-Fu Lin, Te-Chieh Kung and Soon-Jyh Chang, "A Reduced Code Linearity Test Method for Pipelined A/D Converters," Proceedings of the 2008 IEEE Asian Test Symposium, pp.111-116, 2008. (November 24-27, 2008, Sapporo, Japan)
  68. Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A 2-GS/s 6-bit Flash ADC with Offset Calibration," Proceedings of the 2008 IEEE Asian Solid-State Circuits Conference, pp.385-388, 2008. (November 3-5, 2008, Fukuoka, Japan)
  69. Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A Power-Efficient 0.8-V, 9-bit, 20-MS/s Pipelined ADC with Opamp-Shared Loading-Free Architecture," Proceedings of the 2008 IEEE International Conference on Communications, Circuits and Systems, pp.1172-1175, 2008. (May 25-27, 2008, Xiamen, China)
  70. Hung-Yu Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture," Proceedings of the 2007 IEEE TENCON, no. ThSC-O4.1, 2007. (October 30 - November 2, 2007, Taipei, Taiwan)
  71. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A 5-bit 4.2-GS/s Flash ADC in 0.13-um CMOS Process,"Proceedings of the 2007 IEEE Custom Integrated Circuits Conference, pp.213-216, 2007. (September 16-19, 2007, San Jose, California, USA)
  72. Tung-Hsing Wu, Yi-Lin Tsai and Soon-Jyh Chang, "An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC," Proceedings of the 2007 IEEE International Symposium on VLSI Design, Automation & Test, pp.236-239, 2007. (April 25-27, 2007, Hsinchu, Taiwan)
  73. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang and Soon-Jyh Chang, "An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders," Proceedings of the 2006 IEEE Asia-Pacific Conference on Circuits and Systems, pp.255-258, 2006. (December 4-7, 2006, Singapore)
  74. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Histogram Based Testing Strategy for ADCs,"Proceedings of the 2006 IEEE Asian Test Symposium, pp.51-54, 2006. (November 20-23, 2006, Fukuoka, Japan)
  75. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A Digitally Calibrated Current-Voltage Feedback Transconductor in 0.13-um CMOS Process," Proceedings of the 2006 IEEE Asian Solid-State Circuits Conference, pp.159-162, 2006. (November 13-15, 2006, Hangzhou, China)
  76. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A 6-Bit 2-GS/s Flash Analog-to-Digital Converter in 0.18-um CMOS Process," Proceedings of the 2006 IEEE Asian Solid-State Circuits Conference, pp.351-354, 2006. (November 13-15, 2006, Hangzhou, China)
  77. Zhen-Guo Ding, Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A 12-Bit, 135-MS/s Pipelined ADC Using Open-Loop Constant Gain Amplifier with Radix-Based Calibration," Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference, pp.295-299, 2006. (July 13-14, 2006, Macau, China)
  78. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu and Soon-Jyh Chang, "An Easy Testable 2-D Transform Scheme in H.264 Advanced Video Coders," Proceedings of the 4th Regional Inter-University Postgraduate Electrical & Electronic Engineering Conference, pp.124-128, 2006. (July 13-14, 2006, Macau, China)
  79. Jin-Fu Lin and Soon-Jyh Chang, "A High Speed Pipelined Analog-to-Digital Converter Using Modified Time-Shifted Correlated Double Sampling Technique," Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp.5367-5370, 2006. (May 21-24, 2006, Island of Kos, Greece)
  80. Yen-Ting Liu, Lih-Yih Chiou and Soon-Jyh Chang, "Energy-Efficient Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop," Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp.4329-4332, 2006. (May 21-24, 2006, Island of Kos, Greece)
  81. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST," Proceedings of the 2005 IEEE Asian Solid-State Circuits Conference, pp.65-68, 2005. (November 1-3, 2005, Hsinchu, Taiwan)
  82. Ying-Zu Lin and Soon-Jyh Chang, "A CMOS Current-Voltage Feedback Transconductor with an 80-dB SFDR up to 100MHz," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.945-948, 2004. (December 6-9, 2004, Tainan, Taiwan)
  83. Chih-Haur Huang, Soon-Jyh Chang and Kuen-Jong Lee, "Design of High-Resolution Pipelined Analog-to-Digital Converters Using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.625-628, 2004. (December 6-9, 2004, Tainan, Taiwan)
  84. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "An On-Chip Concurrent High Frequency Analog and Digital Sinusoidal Signal Generator," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.173-176, 2004. (December 6-9, 2004, Tainan, Taiwan)
  85. Chih-Haur Huang, Kuen-Jong Lee and Soon-Jyh Chang, "A Low-Cost Diagnosis Methodology for Pipelined A/D Converters," Proceedings of the 2004 IEEE Asian Test Symposium, pp.296-301, 2004. (November 15-17, 2004, Kenting, Taiwan)
  86. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters," Proceedings of the 2004 IEEE Asian Test Symposium, pp.52-57, 2004. (November 15-17, 2004, Kenting, Taiwan)
  87. Kuen-Jong Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng, "A Sigma-Delta Modulation Based BIST Scheme for A/D Converters," Proceedings of the 2003 IEEE Asian Test Symposium, pp.124-127, 2003. (November 17-19, 2003, Xian, China)
  88. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits," Proceedings of the 2002 IEEE International Mixed-Signal Test Workshop, pp.109-117, 2002. (June 19-21, 2002, Montreux, Switzerland)
  89. Chee-Kian Ong, Yeong-Jar Chang, Soon-Jyh Chang, Jiun-Liang Huang, Kuo-Chan Haung, Kwang-Ting Cheng and Wen-Ching Wu, "An Enhanced BIST Scheme for ADC and Non-monotonic DAC," Proceedings of the 2002 IEEE International Mixed-Signal Test Workshop, pp.171-180, 2002. (June 19-21, 2002, Montreux, Switzerland)
  90. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Proceedings of the 2002 IEEE European Test Workshop, pp.261-266, 2002. (May 26-29, 2002, Corfu, Greece)
  91. Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang and Jwu E Chen, "A DFT for semi-DC fault diagnosis for switched-capacitor circuits," Proceedings of the 1999 IEEE European Test Workshop, pp.58-63, 1999. (May 25-28, 1999, Constance, Germany)
  92. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Functional Test Pattern Generation for CMOS Operational Amplifier," Proceedings of the 1997 IEEE VLSI Test Symposium, pp.267-272, 1997. (April 27 - May 1, 1997, Monterey, California, USA)
  93. Chia‐Hsin Lee, Chih‐Huei Hou, Chun‐Po Huang, Wei‐Hao Tsai and Soon‐Jyh Chang, "A 2.5‐bit/cycle 10‐bit 160‐MS/s SAR ADC in 90‐nm CMOS Process," Proceedings of the 26th VLSI Design/CAD Symposium. (August 4-7, 2015, Hualien, Taiwan)
  94. Yung‐Kai Huang and Soon‐Jyh Chang, "A 10‐bit low‐power 100‐kS/s SAR ADC with LSB boosted technique," Proceedings of the 26th VLSI Design/CAD Symposium. (August 4-7, 2015, Hualien, Taiwan)
  95. Sin‐Yang Lin, Chi‐Yuan Huang, Hao‐Ting Jian, Chao‐Ka Yang, Meng‐ Chun Liu, Chuan‐Yu Sun, Chien‐Hung Tsai, Lih‐Yih Chiou, Soon‐Jyh Chang, and Shuenn‐Yuh Lee, "Applied to the detection and treatment of Parkinson's disease System," Proceedings of the 26th VLSI Design/CAD Symposium. (August 4-7, 2015, Hualien, Taiwan)
  96. Yen-Chi Chen, Yen-Long Lee, Yu-Po Cheng, and Soon-Jyh Chang, "A 0.5-to-4 Gbps continuous rate clock and data recovery circuit with bi-directional frequency detection," Proceedings of the 25th VLSI Design/CAD Symposium. (August 5-8, 2014, Taichung, Taiwan)
  97. Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, and Soon-Jyh Chang, "A comparator-based OTA first-order low-distortion sigma-delta modulator with split data weighted averaging algorithm logic,"
  98. Jih-Ren Goh, Soon-Jyh Chang, and Yen-Long Lee, "A 0.5-3.0 Gb/s dual-edge sampling CES DLL-CDR," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  99. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low Power and High Resolution Pipelined SAR ADC with Loading-Free Architecture," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  100. Chao-Fang Tsai, Soon-Jyh Chang, and Ying-Zu Lin, "A 10-Bit 100-MS/s Power-Efficient Flash SAR ADC,"Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  101. Kai-Tzeng Chiou and Soon-Jyh Chang, "A Speed Enhancing Technique for High-Speed Flash ADCs," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
  102. Peng-Yu Chen, Guan-Ying Huang, Soon-Jyh Chang, and Ya-Ting Shyu, "Temperature Measuring Scheme for Multiple Hotspots in System Chips," Proceedings of the 7th VLSI Test Technology Workshop, S4-2. (July 15-17, 2013, Taipei, Taiwan)
  103. Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, and Shao-Hua Wan, "A 0.5-V 10-bit 100-kS/s Asynchronous SAR ADC With Time-Based Fixed Window," Proceedings of the 23th VLSI Design/CAD Symposium. (August 7-10, 2012, Kenting, Taiwan)
  104. Ting-Zi Chen, Guan-Ying Huang, and Soon-Jyh Chang, "A 10-bit 50-MS/s Asynchronous SAR ADC with Low Input Capacitance," Proceedings of the 23th VLSI Design/CAD Symposium. (August 7-10, 2012, Kenting, Taiwan)
  105. I-Jen Chao, Wei-Chih Chen, Chia-Ming Kuo, Bin-Da Liu, Hsin-Wen Ting, Soon-Jyh Chang and Chun-Yueh Huang, "A Low-Distortion Relaxed-DEM-Timing Delta-Sigma Modulator without Extra Adder in the Quantizer Input," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 2011, Yunlin, Taiwan)
  106. Chien-Liang Kuo and Soon-Jyh Chang, "A 20-MHz On-Chip Relaxation Oscillator," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 20101, Yunlin, Taiwan)
  107. Cheng-Wu Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang and Jai-Ming Lin, "Mismatches-Aware Common-Centroid Placement for Capacitor Arrays," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 2011, Yunlin, Taiwan)
  108. An-Sheng Chao and Soon-Jyh Chang, "A SAR ADC BIST for Linearity Test Time Reduction," Proceedings of the 5th VLSI Test Technology Workshop, pp.59-63, 2011. (July 13-15, 2011, Nantou, Taiwan)
  109. Ren-Li Chen, Soon-Jyh Chang and Hsin-Wen Ting, "A Low-Cost Low-Power Current-Steering DAC for UWB Transceivers," Proceedings of the 21th VLSI Design/CAD Symposium. (August 3-6, 2010, Kaohsiung, Taiwan)
  110. Chao-Fang Tsai, Wan-Jing Li, Peng-Yu Chen, Ying-Zu Lin and Soon-Jyh Chang, "On-Chip Reference Oscillators with Process, Supply Voltage and Temperature Compensation," Proceedings of the 21th VLSI Design/CAD Symposium. (August 3-6, 2010, Kaohsiung, Taiwan)
  111. Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin and Soon-Jyh Chang, "A 10-bit Low Input Capacitance SAR ADC,"Proceedings of the 20th VLSI Design/CAD Symposium. (August 4-7, 2009, Hualien, Taiwan)
  112. Jin-Fu Lin and Soon-Jyh Chang, "An Improved Reduced Code Linearity Test Method for Pipelined A/D Converters,"Proceedings of the 3rd VLSI Test Technology Workshop. (July 15-17, 2009, Nantou, Taiwan)
  113. Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A Digitally Calibrated 5-bit 3.2-GS/s Flash ADC," Proceedings of the 19th VLSI Design/CAD Symposium. (August 5-8, 2004, Kenting, Taiwan)
  114. Jin-Fu Lin, Te-Chieh Kung and Soon-Jyh Chang, "Linearity Testing of the Pipelined ADCs Using the Characteristic Observation Method," Proceedings of the 19th VLSI Design/CAD Symposium. (August 5-8, 2004, Kenting, Taiwan)
  115. Yu-Chang Lien, Hsin-Wen Ting, I-Chun Chen, Soon-Jyh Chang and Bin-Da Liu, "A Low-Cost Sine-Wave Histogram Analyzer for ADC BIST," Proceedings of the 2nd VLSI Test Technology Workshop. (July 16-18, 2008, Tainan, Taiwan)
  116. Te-Chieh Kung, Jin-Fu Lin and Soon-Jyh Chang, "Linearity Testing of the Pipelined ADCs Using the Characteristic Observation Method," Proceedings of the 2nd VLSI Test Technology Workshop. (July 16-18, 2008, Tainan, Taiwan)
  117. Cheng-Wu Lin and Soon-Jyh Chang, "An Automated Synthesis Tool for Fully Differential OPAMPs," Proceedings of the 18th VLSI Design/CAD Symposium. (August 7-10, 2007, Hualien, Taiwan)
  118. Hung-Yu Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture," Proceedings of the 18th VLSI Design/CAD Symposium. (August 7-10, 2007, Hualien, Taiwan)
  119. An-Sheng Chao, Soon-Jyh Chang, Shih-Ming Luo, Steven Huang and Chih-Haur Huang, "Design and Implementation of a Built-in Self-Test Scheme for Phase Lock Loops," Proceedings of the 1st VLSI Test Technology Workshop. (July 26-27, 2007, Hsinchu, Taiwan)
  120. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang and Soon-Jyh Chang, "An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders," Proceedings of the 17th VLSI Design/CAD Symposium. (August 8-11, 2006, Hualien, Taiwan)
  121. Zhen-Guo Ding, Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A Self-Calibrated Pipelined ADC with Open-Loop Constant Gain Amplifier," Proceedings of the 17th VLSI Design/CAD Symposium. (August 8-11, 2006, Hualien, Taiwan)
  122. Ying-Zu Lin and Soon-Jyh Chang, "A Digitally Calibrated CMOS Current-Voltage Feedback Transconductor with an 80-dB SFDR up to 100MHz," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  123. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "A Reconfigurable Sinusoidal Signal Generator for Analog-to-Digital Converter Built-In Self-Test," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  124. Yen-Ting Liu, Lih-Yih Chiou and Soon-Jyh Chang, "Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop for Low Power System," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  125. Jin-Fu Lin and Soon-Jyh Chang, "A 1.8-V 10-Bit 100 MS/S Pipelined ADC using Modified Time-Shifted CDS Technique," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
  126. Ying-Zu Lin and Soon-Jyh Chang, "A High-SFDR and Wide-Bandwidth CMOS Current-Voltage Feedback Transconductor," Proceedings of the 15th VLSI Design/CAD Symposium. (August 10-13, 2004, Kenting, Taiwan)
  127. Chih-Haur Huang, Soon-Jyh Chang and Kuen-Jong Lee, "Design of High-Resolution Pipelined Analog-to-Digital Converters using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique," Proceedings of the 15th VLSI Design/CAD Symposium. (August 10-13, 2004, Kenting, Taiwan)
  128. Kuen-Jong Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng, "A Sigma-Delta Modulation Based BIST Scheme for A/D Converters," Proceedings of the 14th VLSI Design/CAD Symposium. (August 12-15, 2003, Hualien, Taiwan)
  129. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Proceedings of the 12th VLSI Design/CAD Symposium. (August 14-17, 2001, Kuansi, Hsinchu, Taiwan)
  130. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Functional Test Pattern Generation for CMOS Operational Amplifier," Proceedings of the 7th VLSI Design/CAD Symposium, pp.65-68. (August 13-16, 1996, Shihmen Dam, Taoyuan, Taiwan)
Patent
more
less
  1. Soon-Jyh Chang, Tz-Jing Shau, Chung-Ming Huang:SWITCHED CAPACITOR CIRCUIT AND COMPENSATION METHOD THEREOF, AND PIPELINE ANALOG TO DIGITAL CONVERTER, ROC Invention Patient Number I581576,(Filling date:March, 03,2016; Issue date: May, 01,2017)
  2. Soon-Jyh Chang, Yu-Po Cheng, Yen-Long Lee;Chung-Ming Huang:Clock And Data Recovery Circuit And Method For Estimating Jitter Tolerance Thereof, ROC Invention Patent Number I573401.(Filling date:July. 23,2015 ;Issue date:March. 01,2017)
  3. Soon-Jyh Chang, Chung-Wei Hsu, Chih-huei Hou, Wei-Hao Tsai:Analog To Digital Converter System For Residue Oversampling And Method Thereof,ROC Invention Patent Number I561013. (Filling date: Oct. 30,2015; Issue date:Dec. 01,2016)
  4. Soon-Jyh Chang, Che-Hsun Kuo, Chung-Ming Huang: Asychronous Successive Approximation Register ADC, ROC Invention Patent Number I535219.(Filing date: Feb. 12,2014; Issue date: May 21,2016)
  5. Soon-Jyh Chang, Che-Hsun Kuo, Chih-Haur Huang: Pre-amplifier And a Comparator, ROC Invention Patent Number I527370.(Filing date: Jun. 26,2014; Issue date: Mar. 21, 2016)
  6. Soon-Jyh Chang, Jih-Ren Goh, Chung Ming Huang: Duobinary Voltage-Mode Transmitter, ROC Invention Patent Number I514780.(Filing date: Jul. 8,2014; Issue date: Dec. 21,2015)
  7. Soon-Jyh Chang, Guan-Ying Huang , Kuen-Jong Lee , Wen-Yu Su , Chung-Ho Chen, Lih-Yih Chiou ,Chih-Hung Kuo , Chien Hung Tsai , Chia Min Lin : Method for Sensing Multi-point Temperatures Applied to Integrated Circuit Chips and System for The Same, ROC Invention Patent Number I489093.(Filing date: May 16,2013; Issue date: Dec. 1,2014)
  8. Soon-Jyh Chang, Yen-Long Lee, Chung-Ming Huang: Adaptive Switched-Capacitor Equalizer, United States Patent 9088449. (Filing date: Feb. 17, 2014; Issue date: Jul. 21, 2015)
  9. Soon-Jyh Chang, Guan-Ying Huang, Kuen-Jong Lee, Wen-Yu Su, Chung-Ho Chen, Lih-Yih Chiou, Chih-Hung Kuo, Chien-Hung Tsai, Chia-Min Lin: Method for Sensing Multi-point Temperatures Applied to Integrated Circuit Chips and System for the same, ROC Invention Patent Number I489093.(Filing date: May. 16, 2013; Issue date: Dec. 1, 2014)
  10. Soon-Jyh Chang, Guan-Ying Huang, Chung-Ming Huang: Successive Approximation Analog to Digital Converter With A Direct Switching Technique For Capacitor Array Through Comparator Output And Method Thereof, ROC Invention Patent Number I477082.(Filing date: Oct. 19, 2011; Issue date: May. 1, 2013)
  11. Soon-Jyh Chang, Jin-Fu Lin: Multiplying Digital-to-Analog Converter and a Converting Method, ROC Invention Patent Number I456910.(Filing date: Jan. 10, 2011; Issue date: Jul. 16, 2012)
  12. Soon-Jyh Chang, Yen Long Lee, Chung-Ming Huang: Clock and Data Recovery (CDR) Architecture and Phase Detector Thereof, ROC Invention Patent Number I456905.(Filing date: Nov. 3, 2011; Issue date: May. 16, 2013)
  13. Soon-Jyh Chang, Chun-Cheng Liu, Guan-Ying Huang: Successive Approximation Analog-to-Digital Converter Having Auxiliary Prediction Circuit and Method Thereof, ROC Invention Patent Number I454064.(Filing date: Dec. 16, 2010; Issue date: Jul. 1, 2012)
  14. Soon-Jyh Chang, Peng-Yu Chen, Jin-Fu Lin: Low Voltage Bandgap Reference (BGR) Circuit, ROC Invention Patent Number I453894.(Filing date: Nov. 23, 2011; Issue date: Jun. 1, 2013)
  15. Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu: Segmented Analog-to-Digital Converter and Method Thereof, ROC Invention Patent Number I452846.(Filing date: Dec. 16, 2010; Issue date: Jul. 1, 2012)
  16. Soon-Jyh Chang, Ming-Liang Chung, Po-Ying Chen, Chung-Ming Huang: Memory Cell and an Associated Memory Device, ROC Invention Patent Number I446342.(Filing date: Jun. 3, 2010; Issue date: Dec. 26, 2011)
  17. Soon-Jyh Chang, Jin-Fu Lin: Multiplying DAC and a Method Thereof, ROC Invention Patent Number I423595.(Filing date: Nov. 9, 2010; Issue date: May. 16, 2012)
  18. Soon-Jyh Chang, Ming-Liang Chung, Po-Ying Chen, Chung-Ming Huang: Memory Cell and an Associated Memory Device, PROC Invention Patent Number CN102280137B.(Filing date: Jun. 8, 2010; Issue date: Dec. 14, 2011)
  19. Soon-Jyh Chang, Guan-Ying Huang, Chung-Ming Huang: Successive Approximation Analog to Digital Converter with A Direct Switching Technique for Capacitor Array through Comparator Output and Method Thereof, United States Patent 8477058. (Filing date: Oct. 12, 2011; Issue date: Jul. 2, 2013)
  20. Soon-Jyh Chang, Yen Long Lee, Chung-Ming Huang: Clock and Data Recovery (CDR) Architecture and Phase Detector Thereof, United States Patent 8457269. (Filing date: Oct. 27, 2011; Issue date: Jun. 4, 2013)
  21. Soon-Jyh Chang, Chun-Cheng Liu, Guan-Ying Huang: Successive Approximation Analog-to-Digital Converter Having Auxiliary Prediction Circuit and Method Thereof, United States Patent 8416116. (Filing date: Mar. 21, 2011; Issue date: Apr. 9, 2013)
  22. Soon-Jyh Chang, Guan-Ying Huang, Chun-Cheng Liu, Chung-Ming Huang, Jin-Fu Lin, Chih-Haur Huang: Successive Approximation Register ADC with A Window Predictive Function, United States Patent 8390501. (Filing date: Apr. 28, 2011; Issue date: Mar. 5, 2013)
  23. Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu: Subrange Analog-to-Digital Converter and Method Thereof, United States Patent 8310388. (Filing date: Mar. 17, 2011; Issue date: Nov. 13, 2012 )
  24. Soon-Jyh Chang, An-Sheng Chao, Chih-Haur Huang, K.-C. Huang, Shih-Ming Luo: Device for Jitter Measurement and Method Thereof, ROC Invention Patent Number I373621.(Filing date: Jul. 14, 2008; Issue date: Feb. 16, 2009)
  25. Soon-Jyh Chang, Ming-Liang Chung, Po-Ying Chen, Chung-Ming Huang: Memory Cell and an Associated Memory Device, United States Patent 8228705. (Filing date: Apr. 22, 2010; Issue date: Jul. 24, 2012)
  26. Soon-Jyh Chang, Jin-Fu Lin: Multiplying DAC and a Method Thereof, United States Patent 8217819. (Filing date: Nov. 8, 2010; Issue date: Jul. 10, 2012)
  27. Soon-Jyh Chang, Jin-Fu Lin, Chih-Haur Huang: Pseudo-Differential Switched-Capacitor Circuits, PROC Invention Patent Number CN101753104B.(Filing date: Dec. 5, 2008; Issue date: Jun. 23, 2010)
  28. Soon-Jyh Chang, Jin-Fu Lin, Chih-Haur Huang: Successive Approximation ADC with Binary Error Tolerance Mechanism, PROC Invention Patent Number CN101729069B.(Filing date: Oct. 27, 2008; Issue date: Jun. 9, 2010)
  29. Soon-Jyh Chang, An-Sheng Chao, Chih-Haur Huang, K.-C. Huang, Shih-Ming Luo: Device and Method for Jitter Measurement, PROC Invention Patent Number CN101349717B. (Filing date: Jul. 16, 2008; Issue date: Jan. 21, 2009)
  30. An-Sheng Chao,?Soon-Jyh Chang, Kuo-Chan Huang, Chih-Haur Huang, Shih-Ming Luo: Device for Jitter Measurement and Method Thereof, United States Patent 7957923. (Filing date: May 8, 2008; Issue date: Jun. 7, 2011)
  31. Soon-Jyh Chang, Jin-Fu Lin, Chih-Haur Huang: Stage-Resolution Scalable Opamp-Sharing Technique for Pipelined/Cyclic ADC, United States Patent 7924204. (Filing date: Oct. 7, 2008; Issue date: Apr. 12, 2011)
  32. Soon-Jyh Chang, Jin-Fu Lin, Chih-Haur Huang: Integrator-Based Common-Mode Stabilization Technique for Pseudo-Differential Switched-Capacitor Circuits, ROC Invention Patent Number I335130.(Filing date: Nov. 14, 2008; Issue date: May. 16, 2010)
  33. Soon-Jyh Chang, Chun-Cheng Liu, Chih-Haur Huang: Successive Approximation ADC with Binary Error Tolerance Mechanism, United States Patent 7724174. (Filing date: Oct. 7, 2008; Issue date: May 25, 2010)
  34. Soon-Jyh Chang, Jin-Fu Lin, Chih-Haur Huang: Integrator-Based Common-Mode Stabilization Technique for Pseudo-Differential Switched-Capacitor Circuits, United States Patent 7724063. (Filing date: Dec. 2, 2008; Issue date: May 25, 2010)
  35. Soon-Jyh Chang, Chun-Cheng Liu, Chih-Haur Huang: Successive Approximation ADC with Binary Error Tolerance Mechanism. ROC Invention Patent Number I328356.(Filing date: Oct. 3, 2008; Issue date: Apr. 16, 2010)
  36. Bin-Da Liu, Hsin-Wen Ting and Soon-Jyh Chang: Histogram Based Testing Method For Analog-to-Digital Converter. ROC Invention Patent Number I311866.(Filing date: Mar. 20, 2006; Issue date: Oct. 1, 2007)
  37. Soon-Jyh Chang and An-Sheng Chao: An On-Chip Ring Oscillator Based CMOS Temperarure Sensor. ROC Invention Patent Number I292474.(Filing date: Mar. 28, 2006; Issue date: Oct. 1, 2007)
Others
more
less
  1. On High Safety and Easily Integrated Analog-to-digital Converter for Car Electronics (2016/08/01~2018/07/31)(NSC 105-2221-E-006-240-MY3)
  2. Research on Design and Implementation for Low Energy Consumption and Easier Integration SAR ADC (2015/05/01~2016/04/31)(NSC 104-2220-E006-012)
  3. Design Methodology of Dynamic Voltage and Frequency Scaling for 3D ICs with Floorplanning and Debugging - Subproject 3: Research on Design Techniques for Temperature Sensing and Clocking Circuits in 3D Chips (2013/08/01 - 2016/07/31) (NSC 102-2221-E-006-263-MY3)
  4. Research on Design and Implementation for Ultra Low Energy Consumption Analog-to-Digital Converters (2/2) (2013/05/01 - 2014/04/30) (NSC 102-2220-E-006 -015)
  5. Design Technology Development of Intelligent Low-Power Multi-Core Systems with Testable/Debuggable Capability: From ESL to Silicon - Subproject 4: Research on Design and Built-in Self-test Techniques for Sensing and Clocking Circuits in Low-power Multi-core Systems (3/3) (2012/08/01 - 2013/07/31) (NSC 101-2220-E-006-005-)
  6. Research on Design and Implementation for Ultra Low Energy Consumption Analog-to-Digital Converters (1/2) (2012/05/01 - 2013/04/30) (NSC 101-2220-E-006 -024)
  7. Design Technology Development of Intelligent Low-Power Multi-Core Systems with Testable/Debuggable Capability: From ESL to Silicon - Subproject 4: Research on Design and Built-in Self-test Techniques for Sensing and Clocking Circuits in Low-power Multi-core Systems (2/3) (2011/08/01 - 2012/07/31) (NSC 100-2220-E-006-005-)
  8. Design Technology Development of Intelligent Low-Power Multi-Core Systems with Testable/Debuggable Capability: From ESL to Silicon - Subproject 4: Research on Design and Built-in Self-test Techniques for Sensing and Clocking Circuits in Low-power Multi-core Systems (1/3) (2010/08/01 - 2011/07/31) (NSC 99-2220-E-006-018-
  9. Research on Design and Design Automation of Low-Power High-Speed Data Converters (2009/08/01 - 2012/07/31) (NSC 98-2221-E-006-156-MY3)
  10. Research on Test and Design Automation of High Speed Data Converters (2007/08/01 - 2009/07/31) (NSC 96-2221-E-006-294-MY2)
  11. Low Power Mobile Devices' Video Processing SOC Design - Subproject 4: Research of Portable Devices' Low Power Video SOC Testing and Design for Testability (3/3) (2007/08/01 - 2008/07/31) (NSC 96-2220-E-006-004-)
  12. Low Power Mobile Devices' Video Processing SOC Design - Subproject 4: Research of Portable Devices' Low Power Video SOC Testing and Design for Testability (2/3) (2006/08/01 - 2007/07/31) (NSC 95-2220-E-006-009-)
  13. Design and Automation of Test Platform for System-On-a-Chip - Subproject 3: Analog and Mixed-Signal Circuits Testing and Test Interface Design in SOC (3/3) (2006/08/01 - 2007/07/31) (NSC 95-2220-E-006-004-)
  14. Low Power Mobile Devices' Video Processing SOC Design - Subproject 4: Research of Portable Devices' Low Power Video SOC Testing and Design for Testability (1/3) (2005/08/01 - 2006/07/31) (NSC 94-2220-E-006-016-)
  15. Design and Automation of Test Platform for System-On-a-Chip - Subproject 3: Analog and Mixed-Signal Circuits Testing and Test Interface Design in SOC (2/3) (2005/08/01 - 2006/07/31) (NSC 94-2220-E-006-010-)
  16. Design and Automation of Test Platform for System-On-a-Chip - Subproject 3: Analog and Mixed-Signal Circuits Testing and Test Interface Design in SOC (1/3) (2004/08/01 - 2005/07/31) (NSC 93-2220-E-006-010-)
  17. Testing and Design-for-Testability for Analog and Mixed-Signal Circuits in System-on-Chip (2003/09/01 - 2004/07/31) (NSC 92-2218-E-006-042)
Projects
  1. On High Safety and Easily Integrated Analog-to-digital Converter for Car Electronics (2016/08/01~2018/07/31)(NSC 105-2221-E-006-240-MY3)
  2. Research on Design and Implementation for Low Energy Consumption and Easier Integration SAR ADC (2015/05/01~2016/04/31)(NSC 104-2220-E006-012)
  3. Design Methodology of Dynamic Voltage and Frequency Scaling for 3D ICs with Floorplanning and Debugging - Subproject 3: Research on Design Techniques for Temperature Sensing and Clocking Circuits in 3D Chips (2013/08/01 - 2016/07/31) (NSC 102-2221-E-006-263-MY3)
  4. Research on Design and Implementation for Ultra Low Energy Consumption Analog-to-Digital Converters (2/2) (2013/05/01 - 2014/04/30) (NSC 102-2220-E-006 -015)
  5. Design Technology Development of Intelligent Low-Power Multi-Core Systems with Testable/Debuggable Capability: From ESL to Silicon - Subproject 4: Research on Design and Built-in Self-test Techniques for Sensing and Clocking Circuits in Low-power Multi-core Systems (3/3) (2012/08/01 - 2013/07/31) (NSC 101-2220-E-006-005-)
  6. Research on Design and Implementation for Ultra Low Energy Consumption Analog-to-Digital Converters (1/2) (2012/05/01 - 2013/04/30) (NSC 101-2220-E-006 -024)
  7. Design Technology Development of Intelligent Low-Power Multi-Core Systems with Testable/Debuggable Capability: From ESL to Silicon - Subproject 4: Research on Design and Built-in Self-test Techniques for Sensing and Clocking Circuits in Low-power Multi-core Systems (2/3) (2011/08/01 - 2012/07/31) (NSC 100-2220-E-006-005-)
  8. Design Technology Development of Intelligent Low-Power Multi-Core Systems with Testable/Debuggable Capability: From ESL to Silicon - Subproject 4: Research on Design and Built-in Self-test Techniques for Sensing and Clocking Circuits in Low-power Multi-core Systems (1/3) (2010/08/01 - 2011/07/31) (NSC 99-2220-E-006-018-
  9. Research on Design and Design Automation of Low-Power High-Speed Data Converters (2009/08/01 - 2012/07/31) (NSC 98-2221-E-006-156-MY3)
  10. Research on Test and Design Automation of High Speed Data Converters (2007/08/01 - 2009/07/31) (NSC 96-2221-E-006-294-MY2)
  11. Low Power Mobile Devices' Video Processing SOC Design - Subproject 4: Research of Portable Devices' Low Power Video SOC Testing and Design for Testability (3/3) (2007/08/01 - 2008/07/31) (NSC 96-2220-E-006-004-)
  12. Low Power Mobile Devices' Video Processing SOC Design - Subproject 4: Research of Portable Devices' Low Power Video SOC Testing and Design for Testability (2/3) (2006/08/01 - 2007/07/31) (NSC 95-2220-E-006-009-)
  13. Design and Automation of Test Platform for System-On-a-Chip - Subproject 3: Analog and Mixed-Signal Circuits Testing and Test Interface Design in SOC (3/3) (2006/08/01 - 2007/07/31) (NSC 95-2220-E-006-004-)
  14. Low Power Mobile Devices' Video Processing SOC Design - Subproject 4: Research of Portable Devices' Low Power Video SOC Testing and Design for Testability (1/3) (2005/08/01 - 2006/07/31) (NSC 94-2220-E-006-016-)
  15. Design and Automation of Test Platform for System-On-a-Chip - Subproject 3: Analog and Mixed-Signal Circuits Testing and Test Interface Design in SOC (2/3) (2005/08/01 - 2006/07/31) (NSC 94-2220-E-006-010-)
  16. Design and Automation of Test Platform for System-On-a-Chip - Subproject 3: Analog and Mixed-Signal Circuits Testing and Test Interface Design in SOC (1/3) (2004/08/01 - 2005/07/31) (NSC 93-2220-E-006-010-)
  17. Testing and Design-for-Testability for Analog and Mixed-Signal Circuits in System-on-Chip (2003/09/01 - 2004/07/31) (NSC 92-2218-E-006-042)
Classes
Students
Current Academic Year Lab Members
Master
Ying-Hsiu Chen
Wei-Li He
Sin-Yu Ciou
Jun-Hui Fu
Ming-Yan Xu
Hsin-Ta Chien
Tsu-Cheng Sheng
Meng-Ju Chiang
Yi-Hu Wang
Yu-Cheng Huang
Kuang-Yu Teng
Guan-Ying Chen
Kai-Cheng Cheng
Wei-Cheng Huang
Chia-Han Wu
Graduates of all Previous Years
Master
100
Chien-Liang Kuo   Nan-Yuan Wang   Min-Hsueh Hsieh   Rong-Sing Chu   Chien-Jung Chen   Chao-Fang Tsai
101
Cheng-Hsun Ho   Gia-Huang Chen   Shao-Hua Wan   Sheng-Hsiung Lin   Ting-Zi Chen   Kun-Yen Hsieh
102
Kai-Hsiang Chiang   Kai-Tzeng Chiou
103
Che-Hsun Kuo   Tien-Feng Hsu   Jih-Ren Goh   Yen-Chi Chen    Jia-Jhang Wu
104
Yu-Bo Cheng   Yung-Kai Huang   Wei-Hao Tsai
105
Wen-Tse Chen   Chih-Huei Hou   Chung-Wei Hsu   Chia-Hsin Lee
106
Ming-Hung Chien
107
Chih-Yuan Kung    Hao-Ting Jian
108
Wen-Chia Lo   Li-Ren Chang    Hua-An Tseng   Yu-Sian Lin   Hao-Sheng Wu   Yao-Tsung Hsieh   Yi-Shen Cheng   Chia-Chuan Lee   Chia-Wei Hu   Huan-Jui Hu   En-Ze Cun
109
Hao-Sheng Wu   Chao-Hsien Ma   Po-Han Lin   Rui-Tong Weng   Yi-Ying Chen
110
Che-Wei Hsu
93
Hsin-Wen Ting
94
Ying-Zu Lin   Chin-Fu Lin   Ren-Li Chen   An-Sheng Chao   Nai-Jhen Cheng
95
Zhen-Guo Ding   Yen-Ting Liu   Cheng-Wu Lin
96
Hung-Yu Huang   Guan-Ying Huang   Shih-Ming Luo   Chi-Ching Chen   Cho-Fan Chen
97
Ya-Ting Shyu   Yu-Chang Lien   Yi-Ting Huang   Su-Ling Huang   Feng-Renn Juang   Wan-Jing Li   Te-Chieh Kung   Pin-Dai Sue   Jeng-Jia Liu
98
Ming-Liang Chung   Tz-Jing Shaw
99
Po-Ying Chen   Meng-Fa Yang   Shih-Shong Huang
Ph.D.
102
Cheng-Wu Lin   Ren-Li Chen   Guan-Ying Huang
103
An-Sheng Chao    Peng-Yu Chen
105
Chun-Po Huang
106
Ya-Ting Shyu   Yen-Long Lee
107
Tzung-Min Tsai
98
Hsin-Wen Ting   Hsin-Hung Ou
99
Chun-Cheng Liu   Jin-Fu Lin   Ying-Zu Lin
Honors
  1. 2016: 104 Semister Good Teaching Faculties
  2. 2013: The great achievement award from the National Program for Intelligent Electronics (NPIE), Taiwan by Professors Kuen-Jong Lee (principle investigator), Chung-Ho Chen, Chien-Hung Tsai, Lih-Yih Chiou, Soon-Jyh Chang, Jai-Ming Lin, and Chih-Hung Kuo
  3. 2012: The 2012 excellent talents award from National Science Council (NSC), Taiwan
  4. 2010: IEEE Tainan Section 2010 Best GOLD Member Award
  5. 2007: The great achievement award from the National Science Council(NSC), Taiwan by Professors Kuen-Jong Lee (principle investigator), Chung-Ho Chen, Ming-Der Shieh, and Soon-Jyh Chang