NCKU EE 教師個人頁面
English Version
盧達生 助理教授
地址
電機系館11樓R92B16
TEL
+886-6-2757575 ext.62427
實驗室網站連結
半導體元件模型實驗室
(R92A53/ext.62400-1662)
學經歷
學歷
2011
美國加州大學博克萊分校電機資訊工程博士
2007
美國加州大學博克萊分校電機資訊工程碩士
2005
國立清華大學電機工程學士
經歷
2015/8-迄今
國立成功大學電機系微電子所助理教授
2011/8-2015/8
美國 IBM 華生實驗室研究員
2010/1-2010/5
美國 IBM 華生實驗室實習研究員
2008/7-2008/9
美國 IBM Fishkill 實習工程師
研究領域
  • FinFET 電晶體之元件模型
  • UTB-SOI 電晶體之元件模型
  • 半導體製程及元件物理模擬
  • 類神經網路之元件與電路 模擬 設計
著作
期刊論文( Journal )
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  1. Y.-F. Hsieh, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D.-D. Lu and K.-H. Kao, “An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications,” IEEE Tran. on Electron Devices, vol. 65, no. 3, Mar. 2018.
  2. A. B. Sachid, Y.-M. Huang, Y.-J. Chen, C.–C. Chen, D. D. Lu, M.-C. Chen, C. Hu, “FinFET with Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits,” IEEE Electron Device Letters, vol. 38, issue 1, Jan 2017.
  3. Angada B. Sachid, Yao-Min Huang, Yi-Ju Chen, Chun-Chi Chen, Darsen D. Lu, Min-Cheng Chen, Chenming Hu (2017, Jan). FinFET with Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits.
  4. P. F. Morin, L. Grenouillet, N. Loubet, A. Pofelski, D. Lu, Q. Liu, E. Augendre, S. Maitrejean, V. Fiori, B. de Salvo, B. Doris, W. Kleemeier, "Mechanical Analyses of Extended and Localized UTBB Stressors Formed with Ge Enrichment Techniques," ECS Transactions, 66 (4), 57-65, 2015
  5. D. Lu, P. Morin, B. Sahu, T. B. Hook, P. Hashemi and A. Scholze et al., “(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations,” ECS Transactions vol. 64, no. 6, pp. 337-345, 2014.
  6. S. J. Han, S. Oida, K. A. Jenkins, D. Lu and Y. Zhu, “Multifinger Embedded T-shaped Gate Graphene RF Transistors with High fMAX/fT Ratio,” IEEE Electron Device Letters, vol. 34, pp. 1340-1342, Oct 2013.
  7. R. Muralidhar, J. Cai, D. J. Frank, P. Oldiges, D. Lu, and I. Lauer, “Meeting the Challenge of Multiple Threshold Voltages in Highly Scaled Undoped FinFETs,” IEEE Transaction on Electron Devices, vol 60, issue 3, pp. 1276-1278, Mar 2013.
  8. Q. Cao, S. J. Han, G. S. Tulevski, Y. Zhu, D. D. Lu, W. Haensch, “Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics.” in Nature nanotechnology, 8(3), 180-186, 2013.
  9. S. Venugopalan, D. D. Lu, Y. Kawakami, P. M. Lee, A. M. Niknejad and C. Hu, “BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations,” Solid-state Electronics 67(1), 79-89, 2012.
  10. S. Khandelwal, Y. S. Chauhan, D. D. Lu, et al., “BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control,” IEEE Tran. on Electron Devices, vol 59, issue 8, pp. 2019-2026, 2012.
  11. M. A. Karim, Y.-S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, et al., “Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs,” IEEE Electron Device Letters, vol. 33, pp. 1306-1308, Sep 2012.
  12. D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, “A Computationally Efficient Compact Model for Fully-Depleted SOI MOSFETs with Independently Controlled Front- and Back-Gates, Solid State Electronics, vol. 62, issue 1, pp. 31-39, Aug 2011.
  13. D. D. Lu, C.-H. Lin, A. M. Niknejad and C. Hu, “Compact Modeling of Variation in FinFET SRAM Cells,” IEEE Design and Test of Computers, vol. 27, no. 2, Mar/Apr 2010.
  14. C.-H. Lin, M. V. Dunga, D. D. Lu, A. M. Niknejad, and C. Hu, " Performance-Aware Corner Model for Design for Manufacturing," IEEE Transaction on Electron Devices, vol, 56, no. 4, April. 2009.
  15. M. V. Dunga, C.-H. Lin, X. Xi, D. D. Lu, A. M. Niknejad, and C. Hu, "Modeling Advanced FET Technology in a Compact Model," IEEE Transaction on Electron Devices, vol. 53, no. 9, Sept. 2006.
  16. An FET with a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications Hsieh, Y. F., Chen, S. H., Chen, N. Y., Lee, W. J., Tsai, J. H., Chen, C. N., Chiang, M. H., Lu, D. D. & Kao, K. H., 2018 Mar 1, In : IEEE Transactions on Electron Devices. 65, 3, p. 855-859
  17. A. B. Sachid, Y.-M. Huang, Y.-J. Chen, C.–C. Chen, D. D. Lu, M.-C. Chen, C. Hu, “FinFET with Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits,” IEEE Electron Device Letters, vol. 38, issue 1, Jan 2017.
會議論文( Conference )
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  1. Darsen D. Lu, Huai-Kuan Zeng, Yi-Ci Wang, Fu-Xiang Liang (2017, Sep). Nvmsim: a Computer-aided-design Tool for Nonvolatile Memory Based Cognitive Computing Hardware. International Confererence on Cognitive Science
  2. Darsen D. Lu, Fu-Xiang Liang, Yi-Ci Wang, and Huai-Kuan Zeng (2017, May). NVMLearn: A Simulation Platform for Non-Volatile-Memory-Based Deep Learning Hardware. International Conference on Applied System Innovation, Sapporo, Japan. MOST 105-2218-E-006-011.
  3. Darsen D. Lu, Angada B. Sachid, Yao-Min Huang, Yi-Ju Chen, Chun-Chi Chen, Min-Cheng Chen, Chenming Hu (2017, Apr). Stressor Design for FinFETs with Air-Gap Spacers. VLSI Technology, Systems and Applications.
  4. T. Yamashita, S. Mehta, V.S. Basker, R. Southwick, A. Kumara, R. Kambhampatib , R. Sathiyanarayanana, J. Johnsona, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Z. Liu, D. Lu, F. Chena, S. Khana, D. Canaperi, B. Haran, J. Stathis, P. Oldiges, C-H. Lin, S. Narasimhaa, A. Bryant, W.K. Hensona, S. Kanakasabapathy, K.V.R.M. Muralia, T. Gow, D. McHerron, H. Bu and M. Khare (2015, Jun). A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in FinFETs. 2015 Symposium on VLSI Technology Digest of Technical Papers, Kyoto, Japan.
  5. D. Lu, K. Cheng, P. Morin, N. Loubet, T. Hook, and D. Guo et al., “Dielectric Isolated FinFET on Bulk Substrate,” IEEE S3S conference, Oct. 2014.
  6. K. Cheng, S. Seo, J. Faltermeier, D. Lu et. al., “Bottom Oxidation through STI (BOTS) – A Novel Approach to Fabricate Dielectric Isolated FinFET on Bulk Substrates,” VLSI Symposium 2014.
  7. A. Khakifirooz et al., “Aggressively Scaled Strained Silicon Directly on Insulator (SSDOI) FinFETs,” Proc. 2013 S3S Conference.
  8. D. D. Lu, J. Chang, M. A. Guillorn, C.-H. Lin, J. Johnson, P. Oldiges and K Rim, “A comparative study of fin-last and fin-first SOI FinFETs,” SISPAD conference, Sept. 2013.
  9. Shu-Jen Han ,Satoshi Oida ,Keith A. Jenkins ,Darsen D. Lu, "High fMAX/fT ratio in multi-finger embedded T-shaped gate graphene transistors, " Device Research Conference, 2013
  10. D. Lu et al., “A Multi-Gate CMOS Compact Model – BSIMMG,” 2010 MOS-AK Workshop.
  11. Chenming Hu, Ali Niknejad, V. Sriramkumar, Darsen Lu, Yogesh Chauhan, Muhammed Kahm, Angada Sachid, "BSIM-IMG: A Turnkey compact model for fully depleted technologies," SOI Conference 2012
  12. D. Lu, S. Venugopalan, T. Morshed, Y. S. Chauhan, C.-H. Lin and M. Dunga, “A Multi-Gate CMOS Compact Model–BSIMMG,” Intl. Workshop on Compact Modeling, Jan 2010
  13. T. H. Morshed, M. V. Dunga, J. Zhang, D. D. Lu, A. M. Niknejad and C. Hu, "Compact Modeling of Flicker Noise Variability in Small Size MOSFETs," International Electron Device Meeting (IEDM), Dec. 2009.
  14. D. D. Lu, C.-H. Lin, S. Yao, W. Xiong, F. Bauer, C. R. Cleavelin, A. M. Niknejad, and C. Hu, “Design of FinFET SRAM Cells using a Statistical Compact Model,” SISPAD conference, Sept. 2009.
  15. C.-H. Lin, M. V. Dunga, D. Lu, A. M. Niknejad and C. Hu, ”Statistical Compact Modeling of Variations in Nano MOSFETs,” Proc. VLSI-TSA, Oct 2008.
  16. D. Lu and C. Hu, “A Compact Model for Parasitic Resistance in FinFETs,” 2009 SRC TECHCON.
  17. C. Hu, M. Dunga, C. H. Lin, D. Lu, A. M. Niknejad, ”Comapct Modeling for New Transistor Structures,” SISPAD 2007, pp. 285-288, Sep 2007.
  18. M. V. Dunga, C.-H. Lin, D. D. Lu, W. Xiong, C. R. Cleavelin, P. Patruno, J.-R. Huang, F.-L. Yang, A. M. Niknejad, and C. Hu, “BSIM-MG: A versatile multi-gate FET model for mixed-signal design,” Symposium on VLSI Technology, June 2007. (Best Student Paper Award)
  19. D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, ” A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation,” International Electron Device Meeting (IEDM), Dec. 2007.
  20. D. Lu, C.-H. Lin, M. Dunga, A. Niknejad and C. Hu, ”A compact model for Asymmetric Multi-gate MOSFETs with Effieicnt Surface Potential Approximations”, 2007 SRC TECHCON (Best in Session)
  21. Darsen Lu, "Enabling Electronic Circuit Simulation for New Semiconductor Technologies -- using the Double-Gate MOS Transistor as an Example, " 2018 Conference on Advanced Topics and Auto Tuning (ATAT) in High-Performance Scientific Computing, Tainan, Taiwan, 2018
專利
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  1. Chung H. Lam, Chung-hsun Lin, Darsen D. Lu, Philip J. Oldiges, ASYMMETRIC FinFET Memory Access Transistor. US patent #9,553,173, February,2017
  2. Kangguo Cheng, Bruce B. Doris, Darsen D. Lu, Ali Khakifirooz, Kern Rim, DIELECTRIC ISOLATED FIN WITH IMPROVED FIN PROFILE. US patent #9,548,213, January,2017
  3. Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim, STRUCTURE AND METHOD FOR COMPRESSIVELY STRAINED SILICON GERMANIUM FINS FOR pFET DEVICES AND TENSILY STRAINED SILICON FINS FOR nFET DEVICES. US patent #9,548,386, January,2017
  4. Cheng Kangguo, Doris Bruce B., Khakifirooz Ali, Lu Darsen D., Reznicek Alexander, Rim Kern, STRAIN RELEASE IN PFET REGIOINS. US patent #9,543,323, January,2017
  5. Hashemi Pouya, Khakifirooz Ali, Lu Darsen, Reznicek Alexander, Schepis Dominic, Lateral Bipolar Junction Transistor Having Graded SiGe Base. US patent #9,525,027, December,2016
  6. Doris Bruce, Khakifirooz Ali, Lu Darsen D., Oldiges Philip, Radiation Tolerant Device Structure. US patent #9,515,171, December,2016
  7. Cheng Kangguo, Khakifirooz Ali, Lu Darsen D., Shahidi Ghavam. Distributed Decoupling Capacitor. US patent #9,455,250, September,2016
  8. Cheng Kangguo, Doris Bruce B., Khakifirooz Ali, Lu Darsen D., Reznicek Alexander and Rim Kern, Semiconductor device including dielectrically isolated finFETs and buried stressor. US patent #9,362,400, June,2016
  9. Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek and Kern Rim, Structure and method for advanced bulk fin isolation. US patent #9,299,618, March, 2016
  10. Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Darsen D. Lu, Alexander Reznicek, Kern Rim, Structure and method to make strained FinFET with improved junction capacitance and low leakage. US Patent #9,276,113,March,2016
  11. Kangguo CHENG Tenko Yamashita Darsen D. Lu Xin Miao. FinFET with reduced parasitic capacitance. US9786737B2 12/13/2015
  12. Chung H. Lam Philip J. Oldiges CHUNG-HSUN LIN Darsen D. Lu. FinFET PCM access transistor having gate-wrapped source and drain regions. US9825094B2 11/30/2015
  13. Cheng Kangguo; Doris Bruce B.; Khakifirooz Ali; Lu Darsen D.; Reznicek Alexander, Engineered substrate and device for co-integration of strained silicon and relaxed silicon; US Patent #9,209,065, Dec. 8, 2015
  14. Wang; Yanfeng, Guo; Dechao, Lu; Darsen, Oldiges; Philip J., Wang; Gan, Wang; Xin, Method and structure for dielectric isolation in a fin field effect transistor. US patent #9,034,715, May 19, 2015
其他
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  1. Y.-S. Chauhan, D. Lu, S. Venugopalan, S. Khandelwal, J. P. Duarte, N. Paydavosi, A. Niknejad and C. Hu, FinFET Modeling for IC Simulation and Design,” Elsevier, 2015.
  2. D. D. Lu, C.-H. Lin, A. M. Niknejad and C. Hu, “Multi-Gate MOSFET Compact Model BSIM-MG,” a chapter in “Comapct Modeling Principles, Techniques and Applications,” Springer, 2010.
  3. Win-San Khwa, Darsen Lu, Chungmen Dou, and Meng-Fan Chang, "Emerging NVM Circuit Techniques and Implementations for Energy-Efficient Systems," a chapter in Beyond-CMOS Technologies for Next Generation Computer Design, Springer, 2018.
研究計劃
  1. 三維記憶體之金氧金整流元件奈米製程
  2. 電阻式記憶體元件特性及可靠度之統計模型
  3. AI創新研究中心專案:應用於生醫影像之類神經電路驗證平台
指導學生
本學年度 實驗室成員
碩士班
梁富翔
洪瑋辰
林啟任
邱柏翰
蔡承憲
葉承叡
博士班
SOURAV DE
MD Aftab Baig
博後
黎黃協
已畢業學生
碩士班
107
洪翊修   王前偉   汪羿齊   邱証彥   杜健暐   林宗翰   曾懷寬
105
陳逸軒
特殊榮譽
  1. 2018 TSIA 半導體獎
  2. 2018 旺宏電子獎座
  3. Who is who in America 2016
  4. UC Berkeley EECS Department Fellowship, Aug 2005
  5. Phi Tau Phi scholastic honor society, June 2005