NCKU EE 教師個人頁面
English Version
盧達生 副教授
地址
電機系館11樓92B09室
TEL
+886-6-2757575 ext.62427
實驗室網站連結
學經歷
學歷
2011
美國加州大學博克萊分校電機資訊工程博士
2007
美國加州大學博克萊分校電機資訊工程碩士
2005
國立清華大學電機工程學士
經歷
2020/12-迄今
國立成功大學電機系微電子所副教授
2015/8-2020/12
國立成功大學電機系微電子所助理教授
2011/8-2015/8
美國 IBM 華生實驗室研究員
2010/1-2010/5
美國 IBM 華生實驗室實習研究員
2008/7-2008/9
美國 IBM Fishkill 實習工程師
研究領域
  • FinFET 電晶體之元件模型
  • UTB-SOI 電晶體之元件模型
  • 半導體製程及元件物理模擬
  • 類神經網路之元件與電路 模擬 設計
著作
期刊論文( Journal )
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  1. M. V. Dunga, C.-H. Lin, X. Xi, D. D. Lu, A. M. Niknejad, and C. Hu, "Modeling Advanced FET Technology in a Compact Model," IEEE Transaction on Electron Devices, vol. 53, no. 9, Sept. 2006, DOI: 10.1109/TED.2005.881001.
  2. C.-H. Lin, M. V. Dunga, D. D. Lu, A. M. Niknejad, and C. Hu, "Performance-Aware Corner Model for Design for Manufacturing," IEEE Transaction on Electron Devices, vol, 56, no. 4, April. 2009, DOI: 10.1109/TED.2008.2011845.
  3. D. D. Lu, C.-H. Lin, A. M. Niknejad and C. Hu, “Compact Modeling of Variation in FinFET SRAM Cells,” IEEE Design and Test of Computers, vol. 27, no. 2, Mar/Apr 2010, DOI: 10.1109/MDT.2010.39.
  4. D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, “A Computationally Efficient Compact Model for Fully-Depleted SOI MOSFETs with Independently Controlled Front- and Back-Gates,” Solid State Electronics, vol. 62, issue 1, pp. 31-39, Aug 2011, DOI: 10.1016/j.sse.2010.12.015.
  5. S. Venugopalan, D. D. Lu, Y. Kawakami, P. M. Lee, A. M. Niknejad and C. Hu, “BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations,” Solid-state Electronics, 67(1), 79-89, 2012, DOI: 10.1016/j.sse.2011.09.001.
  6. S. Khandelwal, Y. S. Chauhan, D. D. Lu, et al., “BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control,” IEEE Tran. on Electron Devices, vol 59, issue 8, pp. 2019-2026, 2012,DOI: 10.1109/TED.2012.2198065.
  7. M. A. Karim, Y.-S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, et al., “Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs,” IEEE Electron Device Letters, vol. 33, pp. 1306-1308, Sep 2012, DOI: 10.1109/LED.2012.2205659
  8. S. J. Han*, S. Oida, K. A. Jenkins, D. Lu and Y. Zhu, “Multifinger Embedded T-shaped Gate Graphene RF Transistors with High fMAX/fT Ratio,” IEEE Electron Device Letters, vol. 34, no. 10, pp. 1340-1342, Oct. 2013, DOI: 10.1109/LED.2013.2276038.
  9. R. Muralidhar*, J. Cai*, D. J. Frank*, P. Oldiges*, D. Lu*, and I. Lauer*, “Meeting the Challenge of Multiple Threshold Voltages in Highly Scaled Undoped FinFETs,” IEEE Transaction on Electron Devices, vol 60, issue 3, pp. 1276-1278, Mar 2013, DOI: 10.1109/TED.2013.2241767.
  10. Q. Cao*, S. J. Han, G. S. Tulevski, Y. Zhu, D. D. Lu, W. Haensch, “Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics.” in Nature Nanotechnology, 8(3), pp. 180-186, 2013, DOI:10.1038/NNANO.2012.257.
  11. A. B. Sachid*, Y.-M. Huang, Y.-J. Chen, C.–C. Chen, D. D. Lu, M.-C. Chen, C. Hu, “FinFET with Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits,” IEEE Electron Device Letters, vol. 38, no. 1, pp. 16-19, Jan 2017, DOI: 10.1109/LED.2016.2628768.
  12. Y.-F. Hsieh*, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D. D. Lu and K.-H. Kao*, “An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications,” IEEE Transaction on Electron Devices, vol. 65, no. 3, pp. 855–850, Mar. 2018, DOI: 10.1109/TED.2018.2791467.
  13. S.-H. Chen, S.-W. Lian, T. R. Wu, T.-R. Chang, J.-M. Liou, D. D. Lu, K.-H. Kao*, N.-Y. Chen, W.-J. Lee and J.-H. Tsai, “Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs,” IEEE Transaction on Electron Devices, vol. 66, no. 6, pp. 2509–2512, Jun. 2019, DOI: 10.1109/TED.2019.2912058.
  14. C.-W. Wang, H. Ku, C.-Y. Chiu, S. De, B.-H. Qiu, C. Shin*, and D. Lu*, “Compact Model for PZT Ferroelectric Capacitors with Voltage Dependent Switching Behavior,” Semiconductor Science and Technology, vol 35, no. 5, Apr. 2020, DOI: 10.1088/1361-6641/ab7c79.
  15. P.-J. Sung, C.-J. Su, S.-H. Lo, F.-K. Hsueh, D. D. Lu, Y.-J. Lee*, T.-S. Chao, “Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter,” IEEE Journal of the Electron Devices Society, vol. 8, pp. 474–480, Apr. 2020, DOI: 10.1109/JEDS.2020.2987005.
  16. D. D. Lu*, S. De, M. A. Baig, B.-H. Qiu and Y.-J. Lee, “A Computationally Efficient Compact Model for Ferroelectric FETs for the Simulation of Online Training of Neural Networks,” Semiconductor Science and Technology, vol. 35, no. 9, Jul. 2020, DOI: 10.1088/1361-6641/ab9bed
  17. W. Lin, D. D. Lu*, Y.-X. Hong and W.-C. Hsu, “Automated Extraction of Barrier Heights for Asymmetric MIM Tunneling Diodes,” Solid State Electronics, vol. 172, no. 107879, Oct. 2020, DOI: 10.1016/j.sse.2020.107879.
  18. S. De, B.-H. Qiu, W.-X. Bu, Md. A. Baig, P.-J. Sung, C.-J. Su, Y.-J. Lee and D. D. Lu*, “Uniform Crystal Formation and Electrical Variability Reduction in Hafnium Oxide Based Ferroelectric Memory by Thermal Engineering,” ACS Applied Electronic Materials, vol. 3, no. 2, 2021, pp. 619—628, DOI: 10.1021/acsaelm.0c00610.
  19. S. De, H.-H. Le, B.-H. Qiu, Md. A. Baig, P.-J. Sung, C.-J. Su, Y.-J. Lee and D.-D. Lu*, “Robust Binary Neural Network Operation from 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses,” IEEE Electron Device Letters, vol. 42, no. 8, Aug. 2021, pp. 1144–1147, DOI: 10.1109/LED.2021.3089621.
  20. P. F. Morin, L. Grenouillet, N. Loubet, A. Pofelski, D. Lu, Q. Liu, E. Augendre, S. Maitrejean, V. Fiori, B. de Salvo, B. Doris, W. Kleemeier, "Mechanical Analyses of Extended and Localized UTBB Stressors Formed with Ge Enrichment Techniques," ECS Transactions, 66 (4), 57-65, 2015
  21. D. Lu, P. Morin, B. Sahu, T. B. Hook, P. Hashemi and A. Scholze et al., “(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations,” ECS Transactions vol. 64, no. 6, pp. 337-345, 2014.
會議論文( Conference )
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  1. M. V. Dunga, C.-H. Lin, D. D. Lu, W. Xiong, C. R. Cleavelin, P. Patruno, J.-R. Huang, F.-L. Yang, A. M. Niknejad, and C. Hu, “BSIM-MG: A versatile multi-gate FET model for mixed-signal design,” Symposium on VLSI Technology, June 2007, DOI: 10.1109/VLSIT.2007.4339727. (Best Student Paper Award)
  2. D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, ”A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation,” International Electron Device Meeting (IEDM), Dec. 2007, DOI: 10.1109/IEDM.2007.4419001.
  3. C.-H. Lin, M. V. Dunga, D. Lu, A. M. Niknejad and C. Hu, ”Statistical Compact Modeling of Variations in Nano MOSFETs,” Proc. VLSI Technology, Systems and Applications (VLSI-TSA), Oct 2008, DOI: 10.1109/VTSA.2008.4530849.
  4. D. D. Lu, C.-H. Lin, S. Yao, W. Xiong, F. Bauer, C. R. Cleavelin, A. M. Niknejad, and C. Hu, “Design of FinFET SRAM Cells using a Statistical Compact Model,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept. 2009, DOI: 10.1109/SISPAD.2009.5290234.
  5. T. H. Morshed, M. V. Dunga, J. Zhang, D. D. Lu, A. M. Niknejad and C. Hu, "Compact Modeling of Flicker Noise Variability in Small Size MOSFETs," International Electron Device Meeting (IEDM), Dec. 2009, DOI: 10.1109/IEDM.2009.5424237.
  6. D. Lu, C.-H. Lin, A. Niknejad and C. Hu, “Multi-Gate MOSFET Compact Model BSIM-MG,” a chapter in Compact Modeling Principles, Techniques, and Applications (ISBN: 978-90-481-8613-6), Springer, 2010, DOI: 10.1007/978-90-481-8614-3_13.
  7. D. D. Lu, J. Chang, M. A. Guillorn, C.-H. Lin, J. Johnson, P. Oldiges and K Rim, “A comparative study of fin-last and fin-first SOI FinFETs,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept. 2013,DOI: 10.1109/SISPAD.2013.6650596.
  8. A. Khakifirooz, R. Sreenivasan, B.N. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E.C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S.M. Mignot, D. Lu et. al., “Aggressively Scaled Strained Silicon Directly on Insulator (SSDOI) FinFETs,” Proceedings of the S3S Conference, pp. 147-150, 2013, DOI: 10.1109/S3S.2013.6716520.
  9. S.-J. Han, S. Oida, K. A. Jenkins, D. D. Lu, "High fMAX/fT ratio in multi-finger embedded T-shaped gate graphene transistors, " IEEE Device Research Conference, 2013, DOI: 10.1109/DRC.2013.6633781.
  10. K. Cheng, S. Seo, J. Faltermeier, D. Lu et. al., “Bottom Oxidation through STI (BOTS) – A Novel Approach to Fabricate Dielectric Isolated FinFET on Bulk Substrates,” Symposium on VLSI Technology, Digest of Technical Papers, June 2014, DOI: 10.1109/VLSIT.2014.6894390.
  11. D. Lu, P. Morin, B. Sahu, T. B. Hook, P. Hashemi and A. Scholze et al., “(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations,” ECS Transactions, vol. 64, no. 6, pp. 337-345, 2014, DOI: 10.1149/06406.0337ecst.
  12. D. Lu, K. Cheng, P. Morin, N. Loubet, T. Hook, and D. Guo et al., “Dielectric Isolated FinFET on Bulk Substrate,” IEEE S3S conference, Oct. 2014, DOI: 10.1109/S3S.2014.7028188.
  13. P. Morin, L. Grenouillet, N. Loubet, A. Pofelski, D. Lu et al., “Mechanical analyses of extended and localized UTBB stressors formed with Ge enrichment techniques,” ECS Transactions, vol. 66, no. 4, pp. 57-65, 2015, DOI: 10.1149/MA2015-01/21/1364.
  14. T. Yamashita, S. Mehta, V.S. Basker, R. Southwick, A. Kumara, R. Kambhampatib, R. Sathiyanarayanana, J. Johnsona, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Z. Liu, D. Lu et al., “A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in FinFETs,” Symposium on VLSI Technology, Digest of Technical Papers, June 2015, DOI: 10.1109/VLSIT.2015.7223659.
  15. D. D. Lu, A. B. Sachid, Y.-M. Huang, Y.-J. Chen, C.-C. Chen, M.-C. Chen, C. Hu, “Stressor Design for FinFETs with Air-Gap Spacers,” VLSI Technology, Systems and Applications (VLSI-TSA), Apr. 2017, DOI: 10.1109/VLSI-TSA.2017.7942485.
  16. D. D. Lu, F.-X Liang, Y.-C. Wang and H.-K. Zeng, “NVMLearn: A Simulation Platform for Non-Volatile-Memory-Based Deep Learning Hardware,” IEEE Intl. Conf. on App. Science & Innovation (ICASI), Sapporo, Japan, May 2017, DOI: 10.1109/ICASI.2017.7988347. (First Prize Paper Award)
  17. D. D. Lu et al., “(Invited) Compact Device Models for FinFET and Beyond,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) Tech. Dig., Kitakyushu, Japan, July 2018, arXiv:2005.02580.
  18. P. J Sung, C. J. Su, D. D. Lu et al., “Fabrication of Ω-gated Negative Capacitance FinFETs and SRAM,” VLSI Technology, Systems and Applications (VLSI-TSA), 2019, DOI: 10.1109/VLSI-TSA.2019.8804663.
  19. S.-W. Chang, P.-J. Sung, T.-Y. Chu, D. D. Lu et al., “First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications,” Proc. IEEE International Electron Devices Meeting (IEDM), 2019, DOI: 10.1109/IEDM19573.2019.8993525.
  20. H.-H. Le, W.-C. Hong, J.-W. Du, T.-H. Lin, Y.-X. Hong, I-H. Chen, W.-J. Lee, N.-Y. Chen and D. D. Lu*, “Ultralow Power Neuromorphic Accelerator for Deep Learning Using Ni/HfO2/TiN Resistive Random Access Memory,” 4th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020, DOI: 10.1109/EDTM47692.2020.9117915.
  21. S. De, Md. A. Baig, B.-H. Qiu, D. Lu*, P.-J. Sung, F.-K. Hsueh, Y.-J. Lee, C.-J. Su, “Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K,” IEEE Device Research Conference (DRC), Ohio State University, Ohio, USA, Jun. 2020, DOI: 10.1109/DRC50226.2020.9135186.
  22. T.-Z. Hong, W.-H. Chang*, A. Agarwal, Y.-T. Huang, C.-Y. Yang, T.-Y. Chu, H.-Y. Chao, Y. Chuang, S.-T. Chung, J.-H. Lin, S.-M. Luo, C.-J. Tsai, M.-J. Li, X.-R. Yu, N.-C. Lin, T.-C. Cho, P.-J. Sung*, C.-J. Su, G.-L. Luo, F.-K. Hsueh, K.-L. Lin, H. Ishii, T. Irisawa, T. Maeda, C.-T. Wu, W. C.-Y. Ma, D.-D. Lu, K.-H. Kao, Y.-J. Lee*, H. J.-H. Chen, C.-L. Lin, R. W. Chuang, K.-P. Huang, S. Samukawa, Y.-M. Li, J.-H. Tarng, T.-S. Chao, M. Miura, G.-W. Huang, W.-F. Wu, J.-Y. Li, J.-M. Shieh, Y.-H. Wang, W.-K. Yeh, “First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT),” Proc. IEEE International Electron Devices Meeting (IEDM), Dec. 2020, DOI: 10.1109/IEDM13553.2020.9372001.
  23. J.-Y. Ciou, S. De*, C.-W. Wang, W. Lin, Y.-J. Lee and D. Lu*, “Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control,” 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Chengdu, China, Apr. 2021, DOI: 10.1109/EDTM50988.2021.9420931.
  24. S. De*, W.-X. Bu, B.-H. Qiu, C.-J. Su, Y.-J. Lee and D. D. Lu*, “Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2021, DOI: 10.1109/VLSI-TSA51926.2021.9440091.
  25. Pei-En Lin, Chia-Hao Cheng, Ching-Hsiang Chang, Cheng-Hsien Tsai, Darsen D. Lu, Yi-Ting Tseng, Ting-Chang Chang, Jen-Sue Chen, “Electroforming-free resistive switching of WOx/ZrOx stack for neuromorphic computing systems,” Materials Challenges for Memory (MCFM), Apr. 11-13, 2021.
  26. S. De*, D. D. Lu*, H.-H. Le, S. Mazumder, Y.-J. Lee*, W.-C. Tseng, B.-H. Qiu, Md. A. Baig, P.-J. Sung, C.-J. Su, C.-T. Wu, W.-F. Wu, W.-K. Yeh, Y.-H. Wang, “Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology,“ Proc. Symposium on VLSI Technology, Kyoto, Japan, Jun. 13-19, 2021.
  27. Darsen D. Lu, Huai-Kuan Zeng, Yi-Ci Wang, Fu-Xiang Liang (2017, Sep). Nvmsim: a Computer-aided-design Tool for Nonvolatile Memory Based Cognitive Computing Hardware. International Confererence on Cognitive Science
  28. D. Lu et al., “A Multi-Gate CMOS Compact Model – BSIMMG,” 2010 MOS-AK Workshop.
  29. Chenming Hu, Ali Niknejad, V. Sriramkumar, Darsen Lu, Yogesh Chauhan, Muhammed Kahm, Angada Sachid, "BSIM-IMG: A Turnkey compact model for fully depleted technologies," SOI Conference 2012
  30. D. Lu and C. Hu, “A Compact Model for Parasitic Resistance in FinFETs,” 2009 SRC TECHCON.
  31. C. Hu, M. Dunga, C. H. Lin, D. Lu, A. M. Niknejad, ”Comapct Modeling for New Transistor Structures,” SISPAD 2007, pp. 285-288, Sep 2007.
  32. D. Lu, C.-H. Lin, M. Dunga, A. Niknejad and C. Hu, ”A compact model for Asymmetric Multi-gate MOSFETs with Effieicnt Surface Potential Approximations”, 2007 SRC TECHCON (Best in Session)
  33. Darsen Lu, "Enabling Electronic Circuit Simulation for New Semiconductor Technologies -- using the Double-Gate MOS Transistor as an Example, " 2018 Conference on Advanced Topics and Auto Tuning (ATAT) in High-Performance Scientific Computing, Tainan, Taiwan, 2018
  34. Darsen D. Lu, "Applications of Memory-Device Compact Models toward Neuromorphic Circuits for Artificial Intelligence," Nano Korea, KINTEX, South Korea, 7/3-5, 2019
專利
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  1. Y. Wang, D. Guo, D. Lu, P. J. Oldiges, G. Wang, X. Wang, “Method and structure for dielectric isolation in a fin field effect transistor,” US patent #9,034,715, May 19, 2015
  2. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, “Engineered substrate and device for co-integration of strained silicon and relaxed silicon,” US patent #9,209,065, Dec. 8, 2015
  3. Kangguo CHENG Tenko Yamashita Darsen D. Lu Xin Miao. FinFET with reduced parasitic capacitance. US9786737B2 12/13/2015
  4. Chung H. Lam Philip J. Oldiges CHUNG-HSUN LIN Darsen D. Lu. FinFET PCM access transistor having gate-wrapped source and drain regions. US9825094B2 11/30/2015
  5. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, K. Rim, “Structure and method to make strained FinFET with improved junction capacitance and low leakage,” US patent #9,276,113, #9,653,541, Mar. 1, 2016
  6. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek and K. Rim, “Structure and method for advanced bulk fin isolation,” US patent #9,299,618, #9,564,439, #9,583,492, Mar. 29, 2016
  7. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek and K. Rim, “Semiconductor device including dielectrically isolated finFETs and buried stressor,” US patent #9,362,400, Jun. 7, 2016
  8. K. Cheng, A. Khakifirooz, D. D. Lu, G. Shahidi, “Distributed decoupling capacitor,” US patent #9,455,250, #10,262,991, Sep. 27, 2016
  9. B. B. Doris, A. Khakifirooz, D. D. Lu, P. Oldiges, “Radiation tolerant device structure,” US patent #9,515,171, Dec. 6, 2016.
  10. P. Hashemi, A. Khakifirooz, D. Lu, A. Reznicek, D. Schepis, “Lateral bipolar junction transistor having graded SiGe base,” US patent #9,525,027, Dec. 20, 2016
  11. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, K. Rim, “Strain release in pFET regions,” US patent #9,543,323, #9,761,610, #9,966,387, Jan. 10, 2017
  12. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, K. Rim, “Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices,” US patent #9,548,386, #9,997,540, Jan. 17, 2017
  13. K. Cheng, B. B. Doris, D. D. Lu, A. Khakifirooz, K. Rim, “Dielectrically isolated fin with improved fin profile,” US patent #9,548,213, #9,917,188, Jan. 17, 2017.
  14. C. H. Lam, C.-H. Lin, D. D. Lu, P. J. Oldiges, “Asymmetric FinFET memory access transistor,” US patent #9,553,173, #9,583,624, Jan. 24, 2017
  15. K. Cheng, T. Yamashita, D. D. Lu, X. Miao, “FinFET with reduced parasitic capacitance,” US patent #9,786,737, #10,177,223, Oct. 10, 2017
  16. C. H. Lam, P. J. Oldiges, C.-H. Lin, D. D. Lu, “FinFET PCM access transistor having gate-wrapped source and drain regions,” US patent #9,825,094, 9,825,094, Nov. 21, 2017
  17. K. Cheng, D. D. Lu, A. Reznicek, B. B. Doris, A. Khakifirooz, K. Rim, “Semiconductor structures having increased channel strain using fin release in gate regions,” US patent #9,954,083, #10,056,474, #10,347,752, Apr. 24, 2018
  18. 盧達生、汪羿齊、曾懷寬 「具有多個控制閘極的快閃記憶體與快閃記憶體陣列裝置」中華民國發明專利 #I664715, Jul. 1, 2019.
  19. D. D. Lu, Y.-C. Wang and H.-K. Zeng, “Flash memory with multiple control gates and flash memory array device made thereof,” US patent #10,622,451, Apr 14, 2020.
其他
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  1. W.-S. Khwa, D. Lu, C. Dou, and M.-F. Chang, “Emerging NVM Circuit Techniques and Implementations for Energy-Efficient Systems,” a chapter in Beyond-CMOS Technologies for Next Generation Computer Design (ISBN: 978-3-319-90385-9), Springer International Publishing, Jan. 2018, DOI: 10.1007/978-3-319-90385-9_4
  2. Y.-S. Chauhan, D. Lu, S. Venugopalan, S. Khandelwal, J. P. Duarte, N. Paydavosi, A. Niknejad and C. Hu, FinFET Modeling for IC Simulation and Design,” Elsevier, 2015.
  3. D. D. Lu, C.-H. Lin, A. M. Niknejad and C. Hu, “Multi-Gate MOSFET Compact Model BSIM-MG,” a chapter in “Comapct Modeling Principles, Techniques and Applications,” Springer, 2010.
研究計劃
  1. 以前瞻非揮發性記憶體為中心適用於大規模平行化之容錯且可重組的異質運算平台-非揮發記憶元件之計算記憶體電路模型
  2. 記憶體計算電路模擬與設計實作及人工智慧應用
  3. 靜態存取式計算記憶體之行為層級模型模擬開發
指導學生
本學年度 實驗室成員
博士班
Aftab Baig
碩士班
蔡瑋慈
謝佳琪
張哲瑋
林侑勳
章富源
蕭琬臻
梁振綱
蔡嘉駿
莊明翰
已畢業學生
博士
110
SOURAV DE
碩士
110
曾偉智   黃筱珊   黃意婷   邱嘉浤   張祐銘   卜偉軒   林修賢   葉承叡
109
林啟任   邱柏翰   蔡承憲
108
梁富翔   洪瑋辰
107
洪翊修   王前偉   汪羿齊   邱証彥   杜健暐   林宗翰   曾懷寬
105
陳逸軒
特殊榮譽
  1. 2018 TSIA 半導體獎
  2. 2018 旺宏電子獎座
  3. Who is who in America 2016
  4. UC Berkeley EECS Department Fellowship, Aug 2005
  5. Phi Tau Phi scholastic honor society, June 2005