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English Version

林家民

教授

地址
奇美系館3樓95305室
Email
電話
06-2757575 ext.62450
實驗室
智慧型電子設計自動化實驗室（另開新視窗）
(R95416 / ext.62400-2862)

學經歷

學歷

2002
國立交通大學資訊科學博士
1998
國立交通大學資訊科學碩士 
1996
國立交通大學資訊科學學士 

經歷

2018-present
國立成功大學電機系 教授
2012-2018
國立成功大學電機系 副教授
2007-2012
國立成功大學電機系 助理教授 
2002-2007
瑞昱半導體研發中心設計自動化部 專案副理

研究領域

  • 實體設計自動化

著作

期刊論文 (Journal)

  1. J.-M. Lin, R.-T. Shen, H.-Y. Hsieh, E.-H. Chu, C.-H. Hsu, Y.-Y. Hsu, Y.-Y. Wang, “Arbitrary-Angle Placement of Non-Rectilinear Bonding Fingers Using a Double-Square Model” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
  2. J.-M. Lin, J.-T. Tsai, H.-L. Chen, “Innovative Approaches to Addressing Challenges in 3D Macro Placement” in ACM Trans. on Design Automation of Electronic Systems (TODAES) 2025
  3. J.-M. Lin, T.-L. Tsai, and T.-C. Tsai, “Multilevel Fixed-outline Component Placement and Graph-based Ball Assignment for System in Package”, in IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), Vol. 31, No. 9, pp. 1308-1319, Aug. 2023.
顯示其餘 22 筆
  1. J.-M. Lin, L.-C. Zane, M.-C. Tsai, Y.-C. Chen, C.-L. Lin and C.-F. Tsai, “PPOM: An Effective Post-Global Placement Optimization Methodology for Better Wirelength and Routability, ” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 30, No. 11, pp. 1783-1793, Nov. 2022.
  2. J. -M. Lin, W. -Y. Chang, H. -Y. Hsieh, Y. -T. Shyu, Y. -J. Chang and J. -M. Lu, “Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC,”in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 29, No. 9, pp. 1652-1664, Sept. 2021
  3. J.-M. Lin, T.-T. Chen, H.-Y. Hsieh, Y.-T. Shyu, Y.-J. Chang, and J.-M. Lu, “Thermal-aware Fixed-outline Floorplanning Using Analytical Models with Thermal-Force Modulation,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 29, No. 5, pp. 985-997, May. 2021.
  4. J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and P.-C. Lu,“Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs,” in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 29, No. 5, pp. 973-984, May. 2021.
  5. J.-M. Lin, Y.-L. Deng, S.-T. Li, B.-H. Yu, L.-Y. Chang and T.-W. Peng, “Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits with Obstacles,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 57-68, Jan. 2019.
  6. J.-M. Lin and J.-A. Yang, “Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D Ics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.36, No.11, pp.1856-1868, Nov. 2017.
  7. Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang, "An Efficient and Effective Methodology to Control Turn-on Sequence of Power Switches for Power Gating Designs," IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD) , Vol. 35, No. 10, pp. 1730-1743, Oct. 2016.
  8. C.-P. Huang, J.-M. Lin , Y.-T. Shyu, and S.-J. Chang, "A Systematic Design Methodology of Asynchronous SAR ADCs," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.23, No. 99, pp.1-14, Nov. 2015.
  9. J.-M. Lin and C.-C. Lin, “Placement Density Aware Power Switch Planning Methodology for Power Gating Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34,No. 5,pp. 766-777, May 2015 .
  10. J.-M. Lin, J.-H. Wu, “F-FM: Fixed-outline Floorplanning Methodology for Mixed-size Modules Considering Voltage-island Constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 11, pp. 1681-1692, Nov. 2014.
  11. Y.-T. Shyu, J.-M. Lin, C.-P. Huang, C.-W. Lin, Y.-Z. Lin and S.-J. Chang, “Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No 4, pp. 624-635, Apr. 2013.
  12. C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.31, No 12, pp.1789-1802, Dec. 2012.
  13. J.-M. Lin and Z.-X. Hung, “SKB-tree: A Fixed-outline Driven Representation for Modern Floorplanning Problems,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 20, No. 3, pp. 473-484, Mar. 2012.
  14. J.-M. Lin and Z-.X. Hung, “UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-placed Modules,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 7, pp. 1034-1044, Jul. 2011.
  15. J.-M Lin and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol 13, No. 2, pp. 288-292, Feb. 2005.
  16. J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 6, pp. 968-980, Jun. 2004.
  17. J.-M. Lin, S.-P. Lin, and Y.-W. Chang, “Corner Sequence: A P-admissible Floorplan Representation with a Worst-case Linear-Time Packing Scheme,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 11, No. 4, pp. 679-686, Aug. 2003.
  18. J.-M. Lin, H.-L. Chen and Y.-W. Chang, “Arbitrarily Shaped Rectilinear Module Placement Using TCG,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 10, No. 6, pp. 886-901, Dec. 2002.
  19. G.-M. Wu, J.-M Lin. and Y.-W. Chang, “Performance-Driven Placement for Dynamically Reconfigurable FPGAs,” ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 7, No. 4, pp. 628-642, Oct. 2002.
  20. J.-M. Lin, H.-E. Yi, and Y.-W. Chang, “Module Placement with Boundary Constraints Using B*-trees,” IEE Proceedings - Circuits, Devices and Systems (EI/SCI), Vol. 149, No. 4, pp. 251-256, Aug. 2002.
  21. G.-M. Wu, J.-M Lin. and Y.-W. Chang, “Generic ILP-Based Approaches for Time-Multiplexed FPGA Partitioning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 10, pp. 1266-1274, Oct. 2001.
  22. Y.-W. Chang, J.-M. Lin, and D. F. Wong, “Matching-Based Algorithm for FPGA Channel Segmentation Design,” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 6, pp. 784 -791, Jun. 2001.

會議論文 (Conference)

  1. J.-M. Lin, C.-H. Wang, L.-T. Fan, and Y. Chou “Structure-Preserving Density Modeling for Electrostatics-Based Analytical Placement” in Proc. of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC),2027
  2. J.-M. Lin, Y.-H. Su, and J.-K. Huang “Congestion Source-Aware Global Placement for Routability Optimization” in Proc. of IEEE International Conference on Computer Aided Design (ICCAD),2026
  3. J.-M. Lin, P.-Y. Chen, Z.-X. Huang, C.-F. Tsai, D.-S. Fu and S.-C. Huang "IR-Drop Aware Global Placement with PDN Optimization and GPU-Accelerated Analysis for Mitigating Global and Local IR-Drop", in Proc of Design Automation Conference (DAC), 2026.
顯示其餘 46 筆
  1. J.-M. Lin, H.-W. Hsu, T. Huang, C.-F. Tsai, D.-S. Fu, and S.-C. Huang, “Efficient Analytical Placement Algorithm with Hybrid-Fence-Region Constraints Using Non-Newtonian Fluid Model,” to be presented in the Proc. of ICCAD 2025.
  2. J.-M. Lin, P.-Y. Chen, M.-C. Tsai, C.-F. Tsai, D.-S. Fu, C.-L. Lin “An Effective Voltage-drop Aware Analytical Placement Approach” in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI),2025.
  3. J.-M. Lin, H.-L. Chen “IR-drop Aware Power Network Synthesis for Power Gating Designs” in Proc. of ACM Great Lakes Symposium on VLSI (GLSVLSI),2025.
  4. J.-M. Lin, Z.-Z. Lee, N.-C. Lin “Effective Macro Placement for Very Large Scale Designs Using MCTS Guided by Pre-Trained RL” in Proc. of IEEE/ACM Design, Automation and Test in Europe Conference and Exhibition (DATE),2025.
  5. J.-M. Lin, Y.-Y. Chang and W.-L. Huang, “Timing-Driven Analytical Placement According to Expected Cell Distribution Range” in Proc. of ACM International Symposium on Physical Design (ISPD),2024.
  6. J.-M. Lin, Y.-C. Chen, W.-Y. Lin, P.-Y. Chen, C.-F. Tsai, D.-S. Fu and C.-L. Lin “An Effective Analytical Placement Approach to Handle Fence Region Constraint,” in Proc. of IEEE/ACM International Conference on Computer Aided Design(ICCAD),2024.
  7. J.-M. Lin, Y.-C. Lin, H. Kung and W.-Y. Lin “HyPlace-3D: A Hybrid Placement Approach for 3D ICs Using Space Transformation Technique,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD),2023.
  8. J.-M. Lin, T.-C. Tsai and R-T. Shen “Routability-driven Orientation-aware Analytical Placement for System in Package” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD),2023.
  9. J.-M. Lin, Y.-T. Chen, Y.-T. Kung and H.-J. Lin “Voltage-Drop Optimization Through Insertion of Extra Stripes To A Power Delivery Network” in Proc. of ACM International Symposium on Physical Design (ISPD), New York, NY U.S.A., pp.35-43, Mar. 2023.
  10. J.-M. Lin, P.-C. Lu, H.-Y. Lin and J.-T. Tsai “A Novel Blockage-avoiding Macro Placement Approach for 3D ICs based on POCS,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD),2022.
  11. J.-M. Lin, H.-Y. Hsieh, H. Kung and H.-J. Lin “Routability-driven Analytical Placement with Precise Penalty Models for Large-Scale 3D ICs,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD),2022.
  12. J.-M. Lin, C.-W. Huang, L.-C. Zane, M.-C. Tsai, C.-F. Tsai and C.-L. Lin,“Routability-driven Global Placer Target on Removing Global and Local Congestion for VLSI Designs”in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), New Orleans, LA U.S.A., pp.1-8, Nov.2021
  13. J.-M. Lin, W.-F. Huang, Y.-C. Chen, Y.-T. Wang and P.-W. Wang,“A Dataflow-aware Analytical Placement Algorithm for Modern Mixed-size Circuit Designs”in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), New Orleans, LA U.S.A., pp.1-8, Nov.2021
  14. J.-M. Lin, Y.-T. Kung, Z.-Y. Huang and I.-R. Chen, “A Fast Power Network Optimization Algorithm for Improving Dynamic IR-Drop, ”in Proc. of International Symposium on Physical Design (ISPD), Virtual Event, U.S.A., pp. 91-98, Mar. 2021.
  15. J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and Y.-C. Chen, “A Novel Macro Placement Approach based on Simulated Evolution Algorithm,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Westminster, CO U.S.A., Nov.2019.
  16. J.-M. Lin, S.-T. Li and Y.-T. Wang, “Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros,”in Proc. of IEEE/ACM Design Automation Conference (DAC), Las Vegas, NV U.S.A., pp. 1-6, June.2019.
  17. J.-M. Lin, T.-T. Chen, Y.-F. Chang, W.-Y. Chang, Y.-T. Shyu, Y.-J. Chang and J.-M. Lu, “A Fast Thermal-Aware Fixed-Outline Floorplanning Methodology Based on Analytical Models,”in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, CA U.S.A., pp. 1-8, Nov.2018.
  18. J.-M. Lin, J.-S. Syu and I.-R. Chen, “Macro-Aware Row-Style Power Delivery Network Design for Better Routability,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, CA U.S.A., pp. 1-8, Nov.2018.
  19. J.-M. Lin and C.-Y. Huang, “General Floorplanning Methodology for 3D ICs with an Arbitrary Bonding Style,” in Proc. of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, pp.1-4, Apr. 2018
  20. J.-M. Lin, C.-Y. Huang and J.-Y. Yang, “Co-Synthesis of Floorplanning and Powerplanning in 3D ICs for Multiple Supply Voltage Designs,” in Proc. of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, pp.1-7, Apr. 2018
  21. J.-M.Lin, B.-H.Yu and L.-Y.Chang, Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits,” in Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, pp.438-443, Jan.2017
  22. J.-M. Lin, B.-Y. Chiu and Y.-F. Chang, “SAINT: Handling Module Folding and Alignment in Fixed-outline Floorplans for 3D ICs,”in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), New Orleans, LA U.S.A., pp.1-7, Nov.2016
  23. J.-M. Lin, C.-Y. Hu, and K.-C. Chan, “Routability-Driven Floorplanning Algorithm for Mixed-Size Modules with Fixed-outline Constraint,” in Proc. of IEEE VLSI Desgin,Automation and Text (VLSI-DAT), Hsinchu, Taiwan, pp. 1-4, Apr. 2015.
  24. J.-M. Lin, C.-C. Lin, Z.-W. Syu, C.-C. Tsai, K. Huang, “Current Density Aware Power Switch Placement Algorithm for Power Gating Designs,” in Proc. of ACM International Symposium on Physical Design (ISPD), Petaluma, CA U.S.A., pp. 85-92, Mar.2014.
  25. K.-C. Chan, J.-M. Lin, C.-J Hsu, “A flexible fixed-outline floorplanning methodology for mixed-size modules,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 435-440, Jan. 2013.
  26. C.-W. Lin, C.-L. Lee, J.-M. Lin, and S.-J. Chang, “Analytical-Based Approach for Capacitor Placement with Gradient Error Compensation and Device Correlation Enhancement in Analog Integrated Circuits,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA U.S.A., pp.635-642, Nov. 2012.
  27. C.-W. Lin, C.-C. Lu, J.-M. Lin, and S.-J. Chang, “Routability-driven Placement Algorithm for Analog Integrated Circuits,” in Proc. of ACM International Symposium on Physical Design (ISPD), Napa, CA U.S.A., pp. 71-78, Mar. 2012.
  28. J.-M. Lin, W.-Y. Cheng, C.-L. Lee, C.-J. Hsu, “Voltage Island-Driven Floorplanning Considering Level shifter Placement,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, pp.443-448, Feb. 2012.
  29. C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits,” in Proc. of ACM/IEEE Design Automation Conference (DAC), San Diego, CA U.S.A., pp. 528-533, Jun. 2011.
  30. C.-W. Lin, C.-C. Lu, C.-P. Huang, S.-J. Chang, and J.-M. Lin, “Routing Aware Placement Algorithms for Modern Analog Integrated Circuits,” in Proc. of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, pp. 1-4, Aug. 2011.
  31. J.-M. Lin and J.-R. Chuang, “Efficient Multi-Layer Obstacle-Avoiding Preferred Direction Rectilinear Steiner Tree Construction,” in Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 527-532, Jan. 2011.
  32. C.-W. Lin, J.-M. Lin, C.-P. Huang, and S.-J. Chang, “Performance-driven Analog Placement Considering Boundary Constraint,” in Proc. of ACM/IEEE Design Automation Conference (DAC), Anaheim, CA U.S.A, pp. 292-297 , Jun. 2010.
  33. J.-M. Lin and H. Hung, “UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, pp. 555-560, Jan. 2010.
  34. J.-M. Lin, G.-M. Wu, Y.-W. Chang, and R.-H. Chuang, “Module Placement with the Symmetry Constraint for Analog Design Using TCG-S,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 1135-1138, Jan. 2004.
  35. J.-M. Lin, S.-R. Pan and Y.-W. Chang, “Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Japan, pp. 851-854, Jan. 2003.
  36. J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” in Proc. of ACM/IEEE Design Automation Conference (DAC), New Orleans, LA U.S.A., pp. 842-847, Jun. 2002.
  37. J.-M. Lin, H.-L. Chen and Y.-W. Chang, “Arbitrary Convex and Concave Rectilinear Module Packing Using TCG,” in Proc. IEEE/ACM Design Automation and Test in Europe Conference (DATE), Paris, France, pp. 69-75, Mar. 2002.
  38. J.-M. Lin and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans,” in Proc. of ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV U.S.A., pp. 764-769, Jun. 2001.
  39. G.-M. Wu, J.-M. Lin and Y.-W. Chang, “ Generic ILP-based Approaches for Time-Multiplexed FPGA Partitioning,” in Proc. of IEEE International Conference on Computer Design (ICCD), Austin, TX U.S.A., pp. 764-769, Sep. 2001.
  40. G.-M. Wu, J.-M. Lin, and Y.-W. Chang, “An Algorithm for Dynamically Reconfigurable FPGAs Placement,” in Proc. of IEEE International Conference on Computer Design (ICCD), Austin, TX U.S.A, pp. 501-504, Sep. 2001.
  41. Y.-W. Chang, J.-M. Lin, and D. F. Wong, “Graph Matching-Based Algorithms for FPGA Segmentation Design,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Santa Clara, CA U.S.A., pp. 34-39, Nov. 1998.
  42. Y.-F. Hsiao, C.-C. Tsai, C.-C. Huang, J.-M. Lin, and C.-C. Lin, “Signal Routing of Power Switches for Low Power Designs,” in Proc. of the 24th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2013.
  43. C.-W. Lin, Y.-C. Chiu, C.-P Huang, S.-J. Chang and J.-M Lin, “Mismatches-Aware Common-Centroid Placement for Capacitor Arrays,” in Proc. of the 22th VLSI Design/CAD Symposium, Yunlin, Taiwan, 2011.
  44. J.-M. Lin and S.-A. Hwang, “Diffusion-Based Approach for Global Placement,” in Proc. of the 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2005.
  45. J.-M. Lin, S.-P. Lin, and Y.-W. Chang, “A P-admissible non-slicing floorplan representation with a worst-case linear-time packing scheme,” in Proc. of The 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001.
  46. J.-M. Lin, S.-R. Pan, and Y.-W. Chang, “A timing-driven matching-based algorithm for array-based FPGA routing,” in Proc. of the 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1999.

專利

  1. Thermal estimation device and thermal estimation method
  2. 溫度估算裝置及溫度估算方法
  3. Simulated evolution based algorithm
顯示其餘 7 筆
  1. CHIP AND POWER PLANNING METHOD
  2. 晶片與電源規劃方法
  3. METHOD OF MACRO PLACEMENT AND A NON-TRANSITORY COMPUTER READABLE MEDIUM THEREOF
  4. 巨集電路的擺置方法及其非暫態電腦可讀取媒體
  5. 適用於混合模組之平面規劃方法FIXED-OUTLINE FLOORPLANNING APPROACH FOR MIXED-SIZE MODULES
  6. 適用於混合模組之平面規劃方法
  7. 積體電路佈線檢查方法(一) (二) (三)

其他

  1. [科技部] 2.5D 多晶粒多物理場感知晶粒擺置與供電協同最佳化。2026~2028
  2. [科技部] 考慮前瞻製程技術且符合業界電路規格之擺置工具開發(2/5)(113-2640-E-006-001)。2025/05/01 ~ 2026/04/30。
  3. [科技部] 考慮前瞻製程技術且符合業界電路規格之擺置工具開發(1/5)(113-2640-E-006-001)。2024/05/01 ~ 2025/04/30。
顯示其餘 15 筆
  1. [科技部] 利用強化學習技巧能最優化線長、可繞度和矽穿孔數量快速且有效的三維晶片擺置方法(112-2221-E-006-179-MY3)。2023/08/01 ~ 2026/07/31。
  2. [科技部] 以全域角度能同步優化多晶片線長與可繞度之3D/2.5D 晶片之擺置方法研究(2/2)(110-2221-E-006-208-MY3)。2022/08/01 ~ 2024/07/31。
  3. [科技部] 以全域角度能同步優化多晶片線長與可繞度之3D/2.5D 晶片之擺置方法研究(1/2)(110-2221-E-006-208-MY3)。2022/08/01 ~ 2023/07/31。
  4. [科技部] 基於人工智慧技術的PCB考慮交錯優化與逃離繞線的接點定位與斜角繞線核心設計(2/2)(110-2622-8-009-006-TA)。2021/01/01 ~ 2021/12/31。
  5. [科技部] 基於人工智慧技術的PCB考慮交錯優化與逃離繞線的接點定位與斜角繞線核心設計(1/2)(109-2622-8-009-014-TA)。2020/01/01 ~ 2020/12/31
  6. [科技部] 在中介層式三維晶片中以線長為導向並考量可繞度之裸晶擺置與藉由較佳微凸塊配置完成封裝繞線 (2/2) (MOST 109-2221-E-006 -147 -MY2)。2020/08/01 ~ 2021/07/31。
  7. [科技部] 在中介層式三維晶片中以線長為導向並考量可繞度之裸晶擺置與藉由較佳微凸塊配置完成封裝繞線 (1/2) (MOST 108-2221-E-006 -147 -MY2)。2019/08/01 ~ 2020/07/31。
  8. [科技部] 適用於給定堆疊模式並能考量可繞度與遵循預先分層模塊限制之積層型三維平面規劃器 (MOST 106-2221-E-006-236-MY2)。2017/08/01 ~ 2019/07/31。
  9. [科技部] 於積層型三維積體電路架構中廣泛的探討可行的實體設計流程 (MOST 105-2221-E-006-245)。2016/08/01 ~ 2017/07/31。
  10. [科技部] 考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法 - 子計畫四：在三維晶片考量多重電壓源之整合型電源線規劃與平面規劃 (NSC 102-2221-E006-278-MY3)。2013/08/01 ~ 2016/07/31。
  11. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發：從電子系統層級至矽晶片層級 - 子計畫五：考量低功率及溫度最佳化之智慧型多核心平面規劃器 (3/3) (NSC 101-2220-E-006-006)。2012/08/01 ~ 2013/07/31。
  12. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發：從電子系統層級至矽晶片層級 - 子計畫五：考量低功率及溫度最佳化之智慧型多核心平面規劃器 (2/3) (NSC 100-2220-E-006-006)。2011/08/01 ~ 2012/07/31。
  13. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發：從電子系統層級至矽晶片層級 - 子計畫五：考量低功率及溫度最佳化之智慧型多核心平面規劃器 (1/3) (NSC 99-2220-E-006-019)。2010/08/01 ~ 2011/07/31。
  14. [科技部] 為了擺置備份邏輯閘之漸進式邏輯閘擺置 (NSC 97-2221-E-006-251-MY2)。2008/08/01 ~ 2010/07/31。
  15. [科技部] 於固定形狀晶片內考量先行擺置區塊之平面規劃 (NSC 97-2218-E-006-006-)。2008/08/01 ~ 2010/07/31。

研究計劃

  1. [產學 宜特] IC 測試板之自動化 Layer and Channel Assignment。2026/08/01~2027/07/31
  2. [產學 國科會] 以生成式人工智慧驅動的混和尺寸晶片擺置方法，實現高效率且可擴展的晶片設計。2026/08/01~2029/07/31
  3. [產學 博梭] 基於DeepSets結構與強化學 習的晶片模塊擺置優化方法。 2025/08/01 ～2028/07/ 30
  4. [產學 日月光] 能滿足給定設計規則且能擺置多顆裸晶並快速評估基板規格及產品尺寸之bond finger擺置器。2025/04 ~ 2026/04
  5. [產學 日月光] 能滿足給定設計規則且允許bond finger被排列成兩排之擺置器。2024/04 ~ 2025/04
  6. [產學 創意電子] 針對混合列高電路設計且能優化 IR drop之全域擺置器。2024/07 ~ 2027/06
  7. [產學 瑞昱] 考慮多重電壓源且能滿足群聚和規律擺置限制之電壓區域規劃(III)。2024/07 ~ 2025/06
  8. [產學 瑞昱] 考慮多重電壓源且能滿足群聚和規律擺置限制之電壓區域規劃(II)。2023/07 ~ 2024/06
  9. [產學 瑞昱] 適用於電源門控電路設計之自動化電源網路合成(II)。2023/07 ~ 2024/06
  10. [產學 日月光] 設計初期之快速元件擺置器與能考量設計規則之bond finger擺置器。2023/04~2024/04
  11. [產學 瑞昱] 考慮多重電壓源且能滿足群聚和規律擺置限制之電壓區域規劃。2022/07 ~ 2023/06
  12. [產學 瑞昱] 適用於電源門控電路設計之自動化電源網路合成。2022/07 ~ 2023/06
  13. [產學 日月光] 能處理系統層級封裝內雙層擺置區域及限制不能擺放區域之元件擺置器。2022/04~2023/04
  14. [產學 工研院] 於三維晶片能同時考慮可繞度和電壓衰退之平面規劃和矽穿孔規劃。2021/01~2021/11
  15. [產學 創意電子] 在多重電壓島設計能考慮 IR-drop 的標準邏輯閘擺置方法。2021/08 ~ 2024/07
  16. [產學 瑞昱] 考慮多重電壓源能最佳化可繞度之模塊擺置原型。2021/07 ~ 2022/06
  17. [產學 日月光] 決定最佳封裝尺寸與最佳訊號 串接位置之系統封裝層級元件擺置器。2021/04~2022/04
  18. [產學 工研院] 依據小晶片技術對佈局空間探索以獲得一個低成本且高效率之加速器。2020/06~2020/12
  19. [產學 日月光] 能遵循分群限制之系統封裝層級裸晶擺置器。2020/04~2021/04
  20. [技轉 日月光] 系統封裝層級裸晶擺置器 。2020/03~2022/03
  21. [產學 奇景] 遵循指定數據路徑的可繞度導向之巨集擺置器。2019/08 ~ 2022/07。
  22. [產學 奇景] 考慮多個功率分布情況的可繞度感知電源網路規劃。2019/08 ~ 2022/07。
  23. [產學 創意電子] 用於數據路徑密集型電路的結構感知標准單元擺置器。2019/08 ~ 2021/07。
  24. [產學 工研院] 能考量熱效應以及熱應力並能處理不同型態模塊的三維晶片平面規劃器。2018/11 ~ 2019/12。
  25. [產學 聯詠] 運算放大器自動電路設計與佈局技術。2017/08 ~ 2019/07。
  26. [產學 奇景] 能最佳化繞線面積並考量區域擁擠度之電源網路合成器。2017/08 ~ 2019/07。
  27. [產學 奇景] 以可繞度為導向且能考量障礙物之巨集電路擺置器。2017/08 ~ 2019/07。
  28. [產學 工研院] 以ARM為主的系統晶片之效能、功耗與熱效應模型演算法開發 (3/3)。2017/12 ~ 2018/11。
  29. [產學 工研院] 以ARM為主的系統晶片之效能、功耗與熱效應模型演算法開發 (2/3)。2016/12 ~ 2017/11。
  30. [產學 工研院] 以ARM為主的系統晶片之效能、功耗與熱效應模型演算法開發 (1/3)。2016/01 ~ 2016/11。

開授課程

115學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

114學年度下學期

  • 資料結構緒論

114學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

113學年度下學期

  • 資料結構緒論

113學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

112學年度下學期

  • 資料結構緒論

112學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

111學年度下學期

  • 資料結構緒論

111學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

109學年度下學期

  • 資料結構緒論

109學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

108學年度下學期

  • 資料結構緒論

108學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

107學年度下學期

  • 資料結構緒論

107學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

106學年度下學期

  • 資料結構緒論

106學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

105學年度下學期

  • 資料結構緒論

105學年度上學期

  • 電子設計自動化概論
  • 奈米積體電路實體設計

104學年度下學期

  • 計算機概論（二）
  • 資料結構緒論

104學年度上學期

  • 奈米積體電路實體設計

103學年度下學期

  • 計算機概論（二）
  • 資料結構緒論

指導學生

本學年度 實驗室成員

碩士班

  • 朱恩翔
  • 林又嘉
  • 樊亮廷
  • 黃丹
  • 胡子揚
  • 黃兆賢
  • 黃偉豪
  • 陳建州
  • 鄭丞淯
  • 蔡家欣
  • 林宸右
  • 蘇秉逸
  • 謝宗翰
  • 黃雋凱
  • 曾致彥
  • 張瑋倫
  • 周易
  • 謝誠獻
  • 呂巽睿
  • 沈侯汰
  • 胡睿喆
  • 凌芷婕
  • 張証宥
  • 曾柏硯
  • 盧昭安
  • 黃伯淳
  • 劉岳晨

已畢業學生

碩士班

98

  • 洪勗
  • 劉埄鎰

99

  • 洪志雄
  • 莊佳儒
  • 曾韋霖
  • 鄭為溢

100

  • 許超然
  • 呂承恩
  • 盧正中
  • 邱彥智
  • 江詩偉
  • 饒秉耕

101

  • 陳韋廷
  • 李玉雲
  • 陳柏嘉

102

  • 李宗霖
  • 蕭育甫
  • 詹凱仲
  • 陳聖文
  • 莊政霖

103

  • 蔡榮陽
  • 吳季恒
  • 林哲均
  • 王郁仁

104

  • 翁子清
  • 徐宗煒
  • 胡智堯
  • 吳佩珊

105

  • 彭德偉
  • 余柏亨
  • 邱柏揚
  • 胡明全

106

  • 張彥夫
  • 陳發大
  • 張立言
  • 黃柏元
  • 楊忠安

107

  • 黃千瑜
  • 李𥯨庭
  • 王奕文
  • 許志勝
  • 陳泰廷
  • 鄧有倫

108

  • 林益勤
  • 陳敬仁
  • 楊雅筑
  • 王怡婷
  • 張煒義
  • 楊智穎
  • 陳奕如

109

  • 黃正毓
  • 劉彥欣
  • 黃崇瑋
  • 陳曜杰
  • 林維新
  • 陳家健

110

  • 蔡宗霖
  • 謝昊芫
  • 黃暘竣
  • 卓世峰
  • 黃瑋凡
  • 詹量棋
  • 龔揚泰
  • 呂柏辰

111

  • 孔瑄
  • 王柏文
  • 林恒璵
  • 陳建宏
  • 陳語甜
  • 蔡旻家

112

  • 陳永宸
  • 林南竹
  • 張佑瑜
  • 林豪嘉
  • 徐崇祐
  • 蔡佳庭
  • 林妤蒨
  • 蔡宗均

113

  • 林維淵
  • 黃昱東
  • 黃偉綸
  • 王祈翔
  • 沈睿霆

114

  • 謝翔宇
  • 徐銘君
  • 王敬閎
  • 蘇育涵
  • 李宗澤
  • 陳星霖
  • 許紘瑋
  • 陳品聿

特殊榮譽

  1. 2026 李國鼎科技與人文講座 李國鼎金質獎
  2. 2022 創惟 論文潛力獎
  3. 2022中國工程師學會高雄分會工程教授獎
  4. 2022中國電機工程師學會傑出電機工程教授獎
  5. 102年度國科會整合型計劃「績優計畫獎」，計畫主持人：李昆忠教授(總主持人)、陳中和教授、邱瀝毅教授、張順志教授、蔡建泓教授、郭致宏教授、蘇文鈺教授、林家民教授。(2013)
  6. 中華民國資訊學會博士論文佳作獎，論文名稱：Transitive Closure Graph Based Representations for VLSI Floorplan Design。(2002)
  7. 首屆台灣 IC 設計學會沈文仁教授年度論文獎，論文名稱："TCG: A transitive closure graph based representation for general floorplans。(2001)
  8. 中國電機工程學會青年論文獎第二名，論文名稱：Matching-based Algorithms for FPGA Segmentation Design。(1998)
  9. 黃瑋凡同學 榮獲《中國電機工程師學會 青年論文獎》第三名
  10. 沈睿霆、王柏智同學 榮獲《2021積體電路電腦輔助設計軟體製作競賽》優等
  11. 呂柏辰同學 榮獲《2022 中國電機工程師學會 青年論文獎》佳作
  12. 沈睿霆、莊文瑞同學 榮獲《2022 積體電路電腦輔助設計軟體製作競賽》優等
  13. 林妤蒨同學 榮獲《中國電機工程師學會 青年論文獎》第二名
  14. 林均致、黃兆賢、朱恩翔同學 榮獲《2023積體電路電腦輔助設計軟體製作競賽》佳作
  15. 林維淵、黃昱東、李宗澤、謝翔宇同學 榮獲《2023積體電路電腦輔助設計軟體製作競賽》佳作
  16. 張瑋倫、趙品倫、蘇秉逸同學 榮獲《2024積體電路電腦輔助設計軟體製作競賽》佳作
  17. 榮獲 成功大學頒發113年度《產學合作成果特優教師 優良獎》