NCKU EE 教師個人頁面
English Version
林家民 教授
地址
奇美系館3樓95305室
TEL
+886-6-2757575 ext.62450
實驗室網站連結
學經歷
學歷
2002
國立交通大學資訊科學博士
1998
國立交通大學資訊科學碩士 
1996
國立交通大學資訊科學學士 
經歷
2018-present
國立成功大學電機系教授
2012-2018
國立成功大學電機系副教授
2007-2012
國立成功大學電機系 助理教授 
2002-2007
瑞昱半導體研發中心設計自動化部 專案副理
研究領域
  • 實體設計自動化
著作
期刊論文( Journal )
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  1. J.-M. Lin, T.-T. Chen, H.-Y. Hsieh, Y.-T. Shyu, Y.-J. Chang, and J.-M. Lu, “Thermal-aware Fixed-outline Floorplanning Using Analytical Models with Thermal-Force Modulation,” to be appeared in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2021.
  2. J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and P.-C. Lu, “Dataflow-aware Macro Placement based on Simulated Evolution Algorithm for Mixed-Size Designs,” to be appeared in IEEE Transactions on Very Large Scale Integration Systems (TVLSI) 2021.
  3. J.-M. Lin, Y.-L. Deng, S.-T. Li, B.-H. Yu, L.-Y. Chang and T.-W. Peng, “Regularity-Aware Routability-Driven Macro Placement Methodology for Mixed-Size Circuits with Obstacles,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 27, No. 1, pp. 57-68, Jan. 2019.
  4. J.-M. Lin and J.-A. Yang, “Routability-Driven TSV-Aware Floorplanning Methodology for Fixed-Outline 3-D Ics,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.36, No.11, pp.1856-1868, Nov. 2017.
  5. Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, Soon-Jyh Chang, "An Efficient and Effective Methodology to Control Turn-on Sequence of Power Switches for Power Gating Designs," IEEE Transactions on COMPUTER-AIDED DESIGN of Integrated Circuits and Systems (TCAD) , Vol. 35, No. 10, pp. 1730-1743, Oct. 2016.
  6. C.-P. Huang, J.-M. Lin , Y.-T. Shyu, and S.-J. Chang, "A Systematic Design Methodology of Asynchronous SAR ADCs," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol.23, No. 99, pp.1-14, Nov. 2015.
  7. J.-M. Lin and C.-C. Lin, “Placement Density Aware Power Switch Planning Methodology for Power Gating Design,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 34,No. 5,pp. 766-777, May 2015 .
  8. J.-M. Lin, J.-H. Wu, “F-FM: Fixed-outline Floorplanning Methodology for Mixed-size Modules Considering Voltage-island Constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, No. 11, pp. 1681-1692, Nov. 2014.
  9. Y.-T. Shyu, J.-M. Lin, C.-P. Huang, C.-W. Lin, Y.-Z. Lin and S.-J. Chang, “Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No 4, pp. 624-635, Apr. 2013.
  10. C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol.31, No 12, pp.1789-1802, Dec. 2012.
  11. J.-M. Lin and Z.-X. Hung, “SKB-tree: A Fixed-outline Driven Representation for Modern Floorplanning Problems,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 20, No. 3, pp. 473-484, Mar. 2012.
  12. J.-M. Lin and Z-.X. Hung, “UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning Considering Pre-placed Modules,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 7, pp. 1034-1044, Jul. 2011.
  13. J.-M Lin and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol 13, No. 2, pp. 288-292, Feb. 2005.
  14. J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 6, pp. 968-980, Jun. 2004.
  15. J.-M. Lin, S.-P. Lin, and Y.-W. Chang, “Corner Sequence: A P-admissible Floorplan Representation with a Worst-case Linear-Time Packing Scheme,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 11, No. 4, pp. 679-686, Aug. 2003.
  16. J.-M. Lin, H.-L. Chen and Y.-W. Chang, “Arbitrarily Shaped Rectilinear Module Placement Using TCG,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 10, No. 6, pp. 886-901, Dec. 2002.
  17. G.-M. Wu, J.-M Lin. and Y.-W. Chang, “Performance-Driven Placement for Dynamically Reconfigurable FPGAs,” ACM Trans. on Design Automation of Electronic Systems (TODAES), Vol. 7, No. 4, pp. 628-642, Oct. 2002.
  18. J.-M. Lin, H.-E. Yi, and Y.-W. Chang, “Module Placement with Boundary Constraints Using B*-trees,” IEE Proceedings - Circuits, Devices and Systems (EI/SCI), Vol. 149, No. 4, pp. 251-256, Aug. 2002.
  19. G.-M. Wu, J.-M Lin. and Y.-W. Chang, “Generic ILP-Based Approaches for Time-Multiplexed FPGA Partitioning,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 10, pp. 1266-1274, Oct. 2001.
  20. Y.-W. Chang, J.-M. Lin, and D. F. Wong, “Matching-Based Algorithm for FPGA Channel Segmentation Design,” IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 20, No. 6, pp. 784 -791, Jun. 2001.
會議論文( Conference )
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  1. J.-M. Lin, Y.-T. Kung, Z.-Y. Huang and I.-R. Chen, “A Fast Power Network Optimization Algorithm for Improving Dynamic IR-Drop, ”in Proc. of International Symposium on Physical Design (ISPD), Virtual Event, U.S.A., pp. 91-98, Mar. 2021.
  2. J.-M. Lin, Y.-L. Deng, Y.-C. Yang, J.-J. Chen and Y.-C. Chen, “A Novel Macro Placement Approach based on Simulated Evolution Algorithm,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Westminster, CO U.S.A., Nov.2019.
  3. J.-M. Lin, S.-T. Li and Y.-T. Wang, “Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between Macros,”in Proc. of IEEE/ACM Design Automation Conference (DAC), Las Vegas, NV U.S.A., pp. 1-6, June.2019.
  4. J.-M. Lin, T.-T. Chen, Y.-F. Chang, W.-Y. Chang, Y.-T. Shyu, Y.-J. Chang and J.-M. Lu, “A Fast Thermal-Aware Fixed-Outline Floorplanning Methodology Based on Analytical Models,”in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, CA U.S.A., pp. 1-8, Nov.2018.
  5. J.-M. Lin, J.-S. Syu and I.-R. Chen, “Macro-Aware Row-Style Power Delivery Network Design for Better Routability,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Diego, CA U.S.A., pp. 1-8, Nov.2018.
  6. J.-M. Lin and C.-Y. Huang, “General Floorplanning Methodology for 3D ICs with an Arbitrary Bonding Style,” in Proc. of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, pp.1-4, Apr. 2018
  7. J.-M. Lin, C.-Y. Huang and J.-Y. Yang, “Co-Synthesis of Floorplanning and Powerplanning in 3D ICs for Multiple Supply Voltage Designs,” in Proc. of IEEE Design, Automation & Test in Europe Conference & Exhibition (DATE), Dresden, Germany, pp.1-7, Apr. 2018
  8. J.-M.Lin, B.-H.Yu and L.-Y.Chang, Regularity-aware routability-driven placement prototyping algorithm for hierarchical mixed-size circuits,” in Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan, pp.438-443, Jan.2017
  9. J.-M. Lin, B.-Y. Chiu and Y.-F. Chang, “SAINT: Handling Module Folding and Alignment in Fixed-outline Floorplans for 3D ICs,”in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), New Orleans, LA U.S.A., pp.1-7, Nov.2016
  10. J.-M. Lin, C.-Y. Hu, and K.-C. Chan, “Routability-Driven Floorplanning Algorithm for Mixed-Size Modules with Fixed-outline Constraint,” in Proc. of IEEE VLSI Desgin,Automation and Text (VLSI-DAT), Hsinchu, Taiwan, pp. 1-4, Apr. 2015.
  11. J.-M. Lin, C.-C. Lin, Z.-W. Syu, C.-C. Tsai, K. Huang, “Current Density Aware Power Switch Placement Algorithm for Power Gating Designs,” in Proc. of ACM International Symposium on Physical Design (ISPD), Petaluma, CA U.S.A., pp. 85-92, Mar.2014.
  12. K.-C. Chan, J.-M. Lin, C.-J Hsu, “A flexible fixed-outline floorplanning methodology for mixed-size modules,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 435-440, Jan. 2013.
  13. C.-W. Lin, C.-L. Lee, J.-M. Lin, and S.-J. Chang, “Analytical-Based Approach for Capacitor Placement with Gradient Error Compensation and Device Correlation Enhancement in Analog Integrated Circuits,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), San Jose, CA U.S.A., pp.635-642, Nov. 2012.
  14. C.-W. Lin, C.-C. Lu, J.-M. Lin, and S.-J. Chang, “Routability-driven Placement Algorithm for Analog Integrated Circuits,” in Proc. of ACM International Symposium on Physical Design (ISPD), Napa, CA U.S.A., pp. 71-78, Mar. 2012.
  15. J.-M. Lin, W.-Y. Cheng, C.-L. Lee, C.-J. Hsu, “Voltage Island-Driven Floorplanning Considering Level shifter Placement,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, pp.443-448, Feb. 2012.
  16. C.-W. Lin, J.-M. Lin, Y.-C. Chiu, C.-P. Huang, and S.-J. Chang, “Common-centroid capacitor placement considering systematic and random mismatches in analog integrated circuits,” in Proc. of ACM/IEEE Design Automation Conference (DAC), San Diego, CA U.S.A., pp. 528-533, Jun. 2011.
  17. C.-W. Lin, C.-C. Lu, C.-P. Huang, S.-J. Chang, and J.-M. Lin, “Routing Aware Placement Algorithms for Modern Analog Integrated Circuits,” in Proc. of IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Seoul, Korea, pp. 1-4, Aug. 2011.
  18. J.-M. Lin and J.-R. Chuang, “Efficient Multi-Layer Obstacle-Avoiding Preferred Direction Rectilinear Steiner Tree Construction,” in Proc. of ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 527-532, Jan. 2011.
  19. C.-W. Lin, J.-M. Lin, C.-P. Huang, and S.-J. Chang, “Performance-driven Analog Placement Considering Boundary Constraint,” in Proc. of ACM/IEEE Design Automation Conference (DAC), Anaheim, CA U.S.A, pp. 292-297 , Jun. 2010.
  20. J.-M. Lin and H. Hung, “UFO: Unified Convex Optimization Algorithms for Fixed-Outline Floorplanning,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Taipei, Taiwan, pp. 555-560, Jan. 2010.
  21. J.-M. Lin, G.-M. Wu, Y.-W. Chang, and R.-H. Chuang, “Module Placement with the Symmetry Constraint for Analog Design Using TCG-S,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, pp. 1135-1138, Jan. 2004.
  22. J.-M. Lin, S.-R. Pan and Y.-W. Chang, “Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing,” in Proc. of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC), Kitakyushu, Japan, pp. 851-854, Jan. 2003.
  23. J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” in Proc. of ACM/IEEE Design Automation Conference (DAC), New Orleans, LA U.S.A., pp. 842-847, Jun. 2002.
  24. J.-M. Lin, H.-L. Chen and Y.-W. Chang, “Arbitrary Convex and Concave Rectilinear Module Packing Using TCG,” in Proc. IEEE/ACM Design Automation and Test in Europe Conference (DATE), Paris, France, pp. 69-75, Mar. 2002.
  25. J.-M. Lin and Y.-W. Chang, “TCG: A Transitive Closure Graph-Based Representation for Non-Slicing Floorplans,” in Proc. of ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV U.S.A., pp. 764-769, Jun. 2001.
  26. G.-M. Wu, J.-M. Lin and Y.-W. Chang, “ Generic ILP-based Approaches for Time-Multiplexed FPGA Partitioning,” in Proc. of IEEE International Conference on Computer Design (ICCD), Austin, TX U.S.A., pp. 764-769, Sep. 2001.
  27. G.-M. Wu, J.-M. Lin, and Y.-W. Chang, “An Algorithm for Dynamically Reconfigurable FPGAs Placement,” in Proc. of IEEE International Conference on Computer Design (ICCD), Austin, TX U.S.A, pp. 501-504, Sep. 2001.
  28. Y.-W. Chang, J.-M. Lin, and D. F. Wong, “Graph Matching-Based Algorithms for FPGA Segmentation Design,” in Proc. of IEEE/ACM International Conference on Computer Aided Design (ICCAD), Santa Clara, CA U.S.A., pp. 34-39, Nov. 1998.
  29. Y.-F. Hsiao, C.-C. Tsai, C.-C. Huang, J.-M. Lin, and C.-C. Lin, “Signal Routing of Power Switches for Low Power Designs,” in Proc. of the 24th VLSI Design/CAD Symposium, Kaohsiung, Taiwan, Aug. 2013.
  30. C.-W. Lin, Y.-C. Chiu, C.-P Huang, S.-J. Chang and J.-M Lin, “Mismatches-Aware Common-Centroid Placement for Capacitor Arrays,” in Proc. of the 22th VLSI Design/CAD Symposium, Yunlin, Taiwan, 2011.
  31. J.-M. Lin and S.-A. Hwang, “Diffusion-Based Approach for Global Placement,” in Proc. of the 16th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2005.
  32. J.-M. Lin, S.-P. Lin, and Y.-W. Chang, “A P-admissible non-slicing floorplan representation with a worst-case linear-time packing scheme,” in Proc. of The 12th VLSI Design/CAD Symposium, Hsinchu, Taiwan, Aug. 2001.
  33. J.-M. Lin, S.-R. Pan, and Y.-W. Chang, “A timing-driven matching-based algorithm for array-based FPGA routing,” in Proc. of the 10th VLSI Design/CAD Symposium, Nangtou, Taiwan, Aug. 1999.
專利
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  1. Chip and Power Planning Method
  2. Method of Macro Placement and a Non-Transitory Computer Readable Medium Thereof
  3. Fixed-outline Floorplanning Approach for Mixed-size Modules
  4. 積體電路佈線檢查方法(一) (二) (三)
其他
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  1. [科技部] 基於人工智慧技術的PCB考慮交錯優化與逃離繞線的接點定位與斜角繞線核心設計(2/2)(110-2622-8-009-006-TA)。2021/01/01 ~ 2021/12/31。
  2. [科技部] 基於人工智慧技術的PCB考慮交錯優化與逃離繞線的接點定位與斜角繞線核心設計(1/2)(109-2622-8-009-014-TA)。2020/01/01 ~ 2020/12/31
  3. [科技部] 在中介層式三維晶片中以線長為導向並考量可繞度之裸晶擺置與藉由較佳微凸塊配置完成封裝繞線 (2/2) (MOST 109-2221-E-006 -147 -MY2)。2020/08/01 ~ 2021/07/31。
  4. [科技部] 在中介層式三維晶片中以線長為導向並考量可繞度之裸晶擺置與藉由較佳微凸塊配置完成封裝繞線 (1/2) (MOST 108-2221-E-006 -147 -MY2)。2019/08/01 ~ 2020/07/31。
  5. [科技部] 適用於給定堆疊模式並能考量可繞度與遵循預先分層模塊限制之積層型三維平面規劃器 (MOST 106-2221-E-006-236-MY2)。2017/08/01 ~ 2019/07/31。
  6. [科技部] 於積層型三維積體電路架構中廣泛的探討可行的實體設計流程 (MOST 105-2221-E-006-245)。2016/08/01 ~ 2017/07/31。
  7. [科技部] 考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法 - 子計畫四:在三維晶片考量多重電壓源之整合型電源線規劃與平面規劃 (NSC 102-2221-E006-278-MY3)。2013/08/01 ~ 2016/07/31。
  8. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級 - 子計畫五:考量低功率及溫度最佳化之智慧型多核心平面規劃器 (3/3) (NSC 101-2220-E-006-006)。2012/08/01 ~ 2013/07/31。
  9. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級 - 子計畫五:考量低功率及溫度最佳化之智慧型多核心平面規劃器 (2/3) (NSC 100-2220-E-006-006)。2011/08/01 ~ 2012/07/31。
  10. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級 - 子計畫五:考量低功率及溫度最佳化之智慧型多核心平面規劃器 (1/3) (NSC 99-2220-E-006-019)。2010/08/01 ~ 2011/07/31。
  11. [科技部] 為了擺置備份邏輯閘之漸進式邏輯閘擺置 (NSC 97-2221-E-006-251-MY2)。2008/08/01 ~ 2010/07/31。
  12. [科技部] 於固定形狀晶片內考量先行擺置區塊之平面規劃 (NSC 97-2218-E-006-006-)。2008/08/01 ~ 2010/07/31。
其他
more
less
  1. [科技部] 基於人工智慧技術的PCB考慮交錯優化與逃離繞線的接點定位與斜角繞線核心設計(2/2)(110-2622-8-009-006-TA)。2021/01/01 ~ 2021/12/31。
  2. [科技部] 基於人工智慧技術的PCB考慮交錯優化與逃離繞線的接點定位與斜角繞線核心設計(1/2)(109-2622-8-009-014-TA)。2020/01/01 ~ 2020/12/31
  3. [科技部] 在中介層式三維晶片中以線長為導向並考量可繞度之裸晶擺置與藉由較佳微凸塊配置完成封裝繞線 (2/2) (MOST 109-2221-E-006 -147 -MY2)。2020/08/01 ~ 2021/07/31。
  4. [科技部] 在中介層式三維晶片中以線長為導向並考量可繞度之裸晶擺置與藉由較佳微凸塊配置完成封裝繞線 (1/2) (MOST 108-2221-E-006 -147 -MY2)。2019/08/01 ~ 2020/07/31。
  5. [科技部] 適用於給定堆疊模式並能考量可繞度與遵循預先分層模塊限制之積層型三維平面規劃器 (MOST 106-2221-E-006-236-MY2)。2017/08/01 ~ 2019/07/31。
  6. [科技部] 於積層型三維積體電路架構中廣泛的探討可行的實體設計流程 (MOST 105-2221-E-006-245)。2016/08/01 ~ 2017/07/31。
  7. [科技部] 考量三維晶片平面規畫與除錯之低功耗動態調整電壓與頻率之設計方法 - 子計畫四:在三維晶片考量多重電壓源之整合型電源線規劃與平面規劃 (NSC 102-2221-E006-278-MY3)。2013/08/01 ~ 2016/07/31。
  8. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級 - 子計畫五:考量低功率及溫度最佳化之智慧型多核心平面規劃器 (3/3) (NSC 101-2220-E-006-006)。2012/08/01 ~ 2013/07/31。
  9. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級 - 子計畫五:考量低功率及溫度最佳化之智慧型多核心平面規劃器 (2/3) (NSC 100-2220-E-006-006)。2011/08/01 ~ 2012/07/31。
  10. [科技部] 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級 - 子計畫五:考量低功率及溫度最佳化之智慧型多核心平面規劃器 (1/3) (NSC 99-2220-E-006-019)。2010/08/01 ~ 2011/07/31。
  11. [科技部] 為了擺置備份邏輯閘之漸進式邏輯閘擺置 (NSC 97-2221-E-006-251-MY2)。2008/08/01 ~ 2010/07/31。
  12. [科技部] 於固定形狀晶片內考量先行擺置區塊之平面規劃 (NSC 97-2218-E-006-006-)。2008/08/01 ~ 2010/07/31。
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研究計劃
  1. [產學 日月光] 能遵循分群限制之系統封裝層級裸晶擺置器。2020/04~2021/04
  2. [產學 工研院] 依據小晶片技術對佈局空間探索以獲得一個低成本且高效率之加速器。2020/06~2020/12
  3. [技轉 日月光] 系統封裝層級裸晶擺置器 。2020/03~2022/03
  4. [產學 奇景] 遵循指定數據路徑的可繞度導向之巨集擺置器。2019/08 ~ 2022/07。
  5. [產學 奇景] 考慮多個功率分布情況的可繞度感知電源網路規劃。2019/08 ~ 2022/07。
  6. [產學 創意電子] 用於數據路徑密集型電路的結構感知標准單元擺置器。2019/08 ~ 2021/07。
  7. [產學 工研院] 能考量熱效應以及熱應力並能處理不同型態模塊的三維晶片平面規劃器。2018/11 ~ 2019/12。
  8. [產學 聯詠] 運算放大器自動電路設計與佈局技術。2017/08 ~ 2019/07。
  9. [產學 奇景] 能最佳化繞線面積並考量區域擁擠度之電源網路合成器。2017/08 ~ 2019/07。
  10. [產學 奇景] 以可繞度為導向且能考量障礙物之巨集電路擺置器。2017/08 ~ 2019/07。
  11. [產學 工研院] 以ARM為主的系統晶片之效能、功耗與熱效應模型演算法開發 (3/3)。2017/12 ~ 2018/11。
  12. [產學 工研院] 以ARM為主的系統晶片之效能、功耗與熱效應模型演算法開發 (2/3)。2016/12 ~ 2017/11。
  13. [產學 工研院] 以ARM為主的系統晶片之效能、功耗與熱效應模型演算法開發 (1/3)。2016/01 ~ 2016/11。
指導學生
本學年度 實驗室成員
碩士班
孔瑄
王思涵
王柏文
林恒璵
陳建宏
陳語甜
蔡旻家
蔡宗霖
謝昊芫
黃暘竣
黃瑋凡
詹量棋
卓世峰
龔揚泰
呂柏辰
已畢業學生
碩士班
109
黃正毓   劉彥欣   黃崇瑋   陳曜杰   林維新   陳家健
108
林益勤   陳敬仁   楊雅筑   王怡婷   張煒義   楊智穎   陳奕如
107
黃千瑜   王奕文   許志勝   陳泰廷   鄧有倫   李𥯨庭
106
張彥夫   陳發大   張立言   黃柏元   楊忠安
105
彭德偉   余柏亨   邱柏揚   胡明全
104
翁子清   徐宗煒   胡智堯   吳佩珊
103
蔡榮陽   吳季恒   林哲均   王郁仁
102
李宗霖   蕭育甫   詹凱仲   陳聖文   莊政霖
101
陳韋廷   陳柏嘉
100
許超然   呂承恩   盧正中   邱彥智   江詩偉   饒秉耕
99
洪志雄   莊佳儒   曾韋霖   鄭為溢
98
洪勗   劉埄鎰
特殊榮譽
  1. 102年度國科會整合型計劃「績優計畫獎」,計畫主持人:李昆忠教授(總主持人)、陳中和教授、邱瀝毅教授、張順志教授、蔡建泓教授、郭致宏教授、蘇文鈺教授、林家民教授。(2013)
  2. 中華民國資訊學會博士論文佳作獎,論文名稱:Transitive Closure Graph Based Representations for VLSI Floorplan Design。(2002)
  3. 首屆台灣 IC 設 計學會沈文仁教授年度論文獎,論文名稱:"TCG: A transitive closure graph based representation for general floorplans。(2001)
  4. 中國電機工程學會青年論文獎第二名,論文名稱:Matching-based Algorithms for FPGA Segmentation Design。(1998)