國立成功大學電機工程學系 教師個人頁面
English Version
陳志方 教授
地址
電機系館12樓92C93室
Email
TEL
06-2757575 ext.62395
實驗室
元件特性量測實驗室
(R92C23/ext.62400-1223)
學經歷
學歷
1998
美國加州大學柏克萊分校電機博士
1995
美國加州大學柏克萊分校電機碩士
1990
國立成功大學電機學士
經歷
2008~now
國立成功大學電機系教授
2011-2014
國立成功大學微電子所所長
2003-2008
國立成功大學電機系副教授
1999-2003
國立成功大學電機系助理教授
1999-1999
台灣積體電路製造公司主任工程師
研究領域
  • 半導體元件
  • 半導體物理
  • 元件可靠度
著作
期刊論文( Journal )
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  1. J. F. Chen, D. H. Yang, C. Y. Lin, and S. Y. Wu, "The impact of mobility degradation and supply voltage on negative bias temperature instability in advanced p-channel metal-oxide-semiconductor field-effect transistors,"Japanese J. Applied Physics, vol. 46, no. 4B, pp. 2011-2014, Apr. 2007.
  2. J. F. Chen, K. M. Wu, J. R. Lee, Y. K. Su, H. C. Wang, Y. C. Lin, and S. L. Hsu, "Characteristics and improvement of hot-carrier reliability in sub-micrometer high-voltage double diffused drain metal-oxide-semiconductor field-effect transistors," Japanese J. Applied Physics, vol. 46, no. 4B, pp. 2019-2022, Apr. 2007.
  3. C. Y. Hu, S. C. Chen, J. F. Chen, S. J. Chang, M. H. Wang, V. Yeh, and J. C. Chen, "Ultra-thin DPN SiON gate dielectrics prepared with various RF powers," J. Vacuum Science and Technology B, vol. 25, no. 4, pp. 1298-1304, Jul./Aug. 2007.
  4. J. F. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, C. M. Liu, and S. L. Hsu, "Off-state avalanche breakdown induced on-resistance degradation in lateral DMOS transistors," IEEE Electron Device Letters, vol. 28, no. 11, pp. 1033-1035, Nov. 2007.
  5. J. R. Lee, J. F. Chen, K. M. Wu, C. M. Liu, and S. L. Hsu, "Effect of hot-carrier-induced interface states distribution on linear drain current degradation in 0.35 um n-type lateral diffused metal-oxide-semiconductor transistors," Applied Physics Letters, vol. 92, p. 103510, Mar. 2008.
  6. J. F. Chen, S. Y. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, and C. M. Liu, "Anomalous increase in hot-carrier-induced threshold voltage shift in n-type drain extended metal-oxide-semiconductor transistors," Applied Physics Letters, vol. 92, p. 113509, Mar. 2008.
  7. J. P. Wang, Y. K. Su, and J. F. Chen, "Effects of surface cleaning on stressvoiding and electromigration of Cu damascene interconnection," IEEE Trans. on Device and Materials Reliability, vol. 8, no. 1, pp. 210-215, Mar. 2008.
  8. K. S. Tian, J. F. Chen, S. Y. Chen, K. M. Wu, J. R. Lee, T. Y. Huang, C. M. Liu, and S. L. Hsu, "An investigation on hot-carrier reliability and degradation index in lateral diffused metal-oxide-semiconductor field-effect transistors," Japanese J. Applied Physics, vol. 47, no. 4, pp. 2641-2644, Apr. 2008.
  9. S. Y. Chen, J. F. Chen, K. M. Wu, J. R. Lee, C. M. Liu, and S. L. Hsu, "Effect of gate voltage on hot-carrier-induced on-resistance degradation in high-voltage n-type lateral diffused metal-oxide-semiconductor transistors," Japanese J. Applied Physics, vol. 47, no. 4, pp. 2645-2649, Apr. 2008.
  10. S. Y. Chen, J. F. Chen, J. R. Lee, K. M. Wu, C. M. Liu, and S. L. Hsu, "Anomalous hot-carrier-induced increase in saturation-region drain current in n-type lateral diffused metal-oxide-semiconductor transistors,"IEEE Trans. on Electron Devices, vol. 55, no. 5, pp. 1137-1142, May 2008.
  11. J. F. Chen, K. S. Tian, S. Y. Chen, J. R. Lee, K. M. Wu, and C. M. Liu, "Mechanism and lifetime prediction method for hot-carrier-induced degradation in lateral diffused metal-oxide-semiconductor transistors," Applied Physics Letters, vol. 92, p. 243501, Jun. 2008.
  12. J. F. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, and C. M. Liu, "Effect of drift-region concentration on hot-carrier-induced Ron degradation in nLDMOS transistors," IEEE Electron Device Letters, vol. 29, no. 7, pp. 771-774, Jul. 2008.
  13. J. F. Chen, K. S. Tian, S. Y. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, and C. M. Liu, "Gate current dependent hot-carrier-induced degradation in LDMOS transistors," Electronics Letters, vol. 44, no. 16, pp. 991-992, Jul. 2008.
  14. J. F. Chen, J. R. Lee, K. M. Wu, T. Y. Huang, and C. M. Liu, "Mechanism and improvement of on-resistance degradation induced by avalanche breakdown in lateral DMOS transistors," IEEE Trans. on Electron Devices,vol. 55, no. 8, pp. 2259-2262, Aug. 2008.
  15. D. H. Yang, J. F. Chen, J. H. Lee, and K. M. Wu, "Dynamic turn-on mechanism of the n-MOSFET under high current stress," IEEE Electron Device Letters, vol. 29, no. 8, pp. 895-897, Aug. 2008.
  16. J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, and C. M. Liu, "On-resistance degradation induced by hot-carrier injection in LDMOS transistors with STI in the drift region," IEEE Electron Device Letters, vol. 29, no. 9, pp. 1071-1073, Sep. 2008.
  17. J. F. Chen, S. Y. Chen, K. M. Wu, and C. M. Liu, "Channel length dependence of hot-carrier-induced degradation in n-type drain extended metal-oxide-semiconductor transistors," Applied Physics Letters, vol. 93, p. 223504, Dec. 2008.
  18. J. F. Chen, S. Y. Chen, K. M. Wu, and C. M. Liu, "Investigation of hot-carrier-induced degradation mechanisms in p-type high-voltage drain extended metal-oxide-semiconductor transistors," Japanese J. Applied Physics, vol. 48, p. 04C039, Apr. 2009.
  19. J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, and C. M. Liu, "Mechanism and modeling of on-resistance degradation in n-type lateral diffused metal-oxide-semiconductor transistors," Japanese J. Applied Physics, vol. 48, p. 04C040, Apr. 2009.
  20. J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, J. R. Shih, and K. Wu, "An investigation on anomalous hot-carrier-induced on-resistance reduction in n-type LDMOS transistors," IEEE Trans. on Device and Materials Reliability, vol. 9, no. 3, pp. 459-464, Sep. 2009.
  21. J. F. Chen, S. Y. Chen, K. M. Wu, J. R. Shih, and K. Wu, "Convergence of hot-carrier-induced saturation-region drain current and on-resistance degradation in drain extended MOS transistors," IEEE Trans. on Electron Devices, vol. 56, no. 11, pp. 2843-2847, Nov. 2009.
  22. J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, J. R. Shih, and K. Wu, "Mechanisms of hot-carrier-Induced threshold voltage shift in high-voltage p-type LDMOS transistors," IEEE Trans. on Electron Devices, vol. 56, no. 12, pp. 3203-3206, Dec. 2009.
  23. C. Y. Hu, J. F. Chen, S. C. Chen, S. J. Chang, C. P. Lee, and T. H. Lee, "Improved poly gate engineering for 65 nm low power CMOS technology," J. of The Electrochemical Society, vol. 157, no. 1, pp. H38-H43, Jan. 2010.
  24. C. Y. Hu, J. F. Chen, S. C. Chen, S. J. Chang, S. M. Wang, C. P. Lee, and K. M. Lee, "Shallow trench isolation stress modification by optimal shallow trench isolation process for sub-65-nm low power complementary," J. Vacuum Science Technology B, vol. 28, no. 2, pp. 391-397, Mar. 2010.
  25. C. Y. Hu, J. F. Chen, S. C. Chen, S. J. Chang, K. M. Lee, and C. P. Lee, "Improvement of poly-pimple-induced device mismatch on 6T-SRAM at 65-nm CMOS technology," IEEE Trans. on Electron Devices, vol. 57, no. 4, pp. 956-959, Apr. 2010.
  26. C. Y. Hu, J. F. Chen, S. C. Chen, S. J. Chang, K. M. Lee, and C. P. Lee, "Ultrathin DPN STI SiON liner for 40 nm low-power CMOS technology," Solid-State Electronics, vol. 54, no. 5, pp. 564-567, May 2010.
  27. D. H. Yang, J. F. Chen, K. M. Wu, J. R. Shih, and J. H. Lee, "The direct evidence of substrate potential propagation in a gate-grounded NMOS," Solid-State Electronics, vol. 54, no. 7, pp. 728-731, Jul. 2010.
  28. J. F. Chen, C. R. Yan, Y. C. Lin, J. J. Fan, S. F. Yang, and W. C. Shih, "Analysis of GIDL-induced off-state breakdown in high-voltage depletion-mode nMOSFETs," IEEE Trans. on Electron Devices, vol. 58, no. 6, pp. 1608-1613, Jun. 2011.
  29. P. C. Huang, S. L. Wu, S. J. Chang, Y. T. Huang, J. F. Chen, C. T. Lin, M. Ma, and O. Cheng, "Characteristics of Si/SiO2 interface properties for CMOS fabricated on hybrid orientation substrate using amorphization/templated recrystallization (ATR) method," IEEE Trans. on Electron Devices, vol. 58, no. 6, pp. 1635-1642, Jun. 2011.
  30. C. R. Yan, J. F. Chen, Y. J. Lee, Y. J. Liao, C. Y. Lin, C. Y. Chen, Y. C. Lin, and H. H. Chen, "Extraction and Analysis of Interface States in 50-nm NAND Flash Devices, " IEEE Trans. on Electron Devices, vol. 60, no. 3, pp. 992-997, Mar. 2013.
  31. C. R. Yan, J. F. Chen, Y. J. Lee, C. Y. Lin, H. T. Hsu, Y. J. Liao, M. T. Yang, C. Y. Chen, Y. C. Lin, and H. H. Chen, "Characteristics of Lateral Duffsed Metal-Oxide-Semiconductor Transistors with Lightly Doped Drain Implantation through Gradual Screen Oxide," Japanese J. Applied Physics, vol. 52, p.04CC07, Apr. 2013
  32. C. R. Yan, J. F. Chen, Y. J. Lee, W. S. Huang, M. J. Huang, C. Y. Chen, Y. C. Lin, K. F. Chang, and H. H. Chen, "Characteristics of sub-50nm NAND flash devices with various self-aligned shallow trench isolation depths," Japanese J. Applied Physics, vol. 52, p. 11NA06, Nov. 2013.
  33. S. C. Tsai, S. L. Wu, J. F. Chen, B. C. Wang, P. C. Huang, K. S. Tsai, T. H. Kao, C. W. Yang, C. G. Chen, K. Y. Lo, O. Cheng, and Y. K. Fang, "Investigation of low-frequency noise characterization of 28-nm high-k pMOSFET with embedded SiGe source/drain," J. Nanomaterials, vol. 2014, p. 787132, Mar. 2014.
  34. S. C. Tsai, S. L. Wu, J. F. Chen, B. C. Wang, P. C. Huang, K. S. Tsai, T. H. Kao, C. W. Yang, C. G. Chen, K. Y. Lo, O. Cheng, and Y. K. Fang, "Investigation of low-frequency noise characterization of 28-nm high-k pMOSFET with embedded SiGe source/drain," J. Nanomaterials, vol. 2014, p. 787132, Mar. 2014.
  35. J. F. Chen, T. H. Chen, and D. R. Ai, "Two-stage hot-carrier induced degradation of p-type LDMOS transistors," Electronics Letters, vol. 50, no. 23, pp. 1751-1753, Nov. 2014.
  36. P. C. Huang, J. F. Chen, S. C. Tsai, S. L. Wu, K. S. Tsai, T. H. Kao, Y. K. Fang, C. M. Lai, C. W. Hsu, Y. W. Chen, and O. Cheng, "Impact of uniaxial strain on random telegraph noise in high-k/metal gate pMOSFETs," IEEE Trans. on Electron Devices, vol. 62, no. 3, pp. 988-993, Mar. 2015.
  37. J. F. Chen, C. P. Chang, Y. M. Liu, Y. L Tsai, H. T. Hsu, C. Y. Chen, and H. P. Hwang, "Drift region doping effects on characteristics and reliability of high-voltage n-type metal-oxide-semiconductor transistors," Japanese J. Applied Physics, vol. 55, p. 01AD03, Jan. 2016.
  38. J. F. Chen, T. J. Ai, Y. L. Tsai, H. T. Hsu, C. Y. Chen, and H. P. Hwang, "Analysis of high-voltage metal-oxide-semiconductor transistors with gradual junction in the drift region," Japanese J. Applied Physics, vol. 55, p. 08PD04, Aug. 2016.
會議論文( Conference )
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  1. J. P. Wang, Y. K. Su, and J. F. Chen, "Influence of surface cleaning on stressvoiding and electromigration of Cu damascene interconnection," Proc. 45rd IEEE International Reliability Physics Symposium (IRPS), pp. 646-647, Apr. 2007.
  2. J. F. Chen, S. Y. Chen, K. S. Tian, K. M. Wu, Y. K. Su, C. M. Liu, and S. L. Hsu, "Effects of drift-region design on the reliability of integrated high-voltage LDMOS transistors," Proc. 2007 IEEE International Conf. on IC Design and Technology, pp. 121-124, May 2007.
  3. K. S. Tian, J. F. Chen, W. C. Wang, S. Y. Chen, K. M. Wu, J. R. Lee, C. M. Liu, and S. L. Hsu, "Mechanism and reliability index of hot-carrier degradation in LDMOS transistors," Ext. Abs. 2007 International Conference on Solid State Devices and Materials (SSDM), pp. 452-453, Sep. 2007.
  4. S. Y. Chen, J. F. Chen, K. M. Wu, J. R. Lee, C. M. Liu, and S. L. Hsu, "Anomalous hot-carrier-induced on-resistance degradation in high-voltage LDMOS transistors," Ext. Abs. 2007 International Conference on Solid State Devices and Materials (SSDM), pp. 454-455, Sep. 2007.
  5. J. F. Chen, J. R. Lee, K. M. Wu, and C. M. Liu, "Impact of hot-hole injection on the characteristics of high-voltage MOS transistors," Proc. 13th International Symp. on Electrets, pp. 77, Sep. 2008.
  6. J. F. Chen, J. R. Lee, S. Y. Chen, K. S. Tian, K. M. Wu, and C. M. Liu, "Hot-carrier-induced degradation in p-type high-voltage DEMOS transistors," Ext. Abs. 2008 International Conference on Solid State Devices and Materials (SSDM), pp. 430-431, Sep. 2008.
  7. K. S. Tian, J. F. Chen, S. Y. Chen, J. R. Lee, K. M. Wu, and C. M. Liu, "Effect of hot-carrier-induced hole trapping on n-type LDMOS transistors," Ext. Abs. 2008 International Conference on Solid State Devices and Materials (SSDM), pp. 444-445, Sep. 2008.
  8. J. F. Chen, K. S. Tian, S. Y. Chen, K. M. Wu, and C. M. Liu, "Effect of NDD dosage on hot-carrier reliability in DMOS transistors," Proc. 10th International Symp. on Quality Electronic Design, pp. 226-229, Mar. 2009.
  9. J. F. Chen, K. W. Lin, S. Y. Chen, K. M. Wu, J. R. Shih, and K. Wu, "Anomalous hot-carrier-induced saturation drain current degradation in DEMOS transistors," Ext. Abs. 2009 International Conference on Solid State Devices and Materials (SSDM), pp. 412-413, Oct. 2009.
  10. P. C. Huang, S. L. Wu, S. J. Chang, J. F. Chen, Y. T. Huang, D. G. Hong, C. Y. Chang, C. Y. Wu, C. T. Lin, M. Ma, and O. Cheng, "Evaluation of Si/SiO2 interface properties for CMOS fabricated on hybrid orientation substrate with amorphization/templated recrystallization method," Ext. Abs. 2010 International Conference on Solid State Devices and Materials (SSDM), pp. 189-190, Sep. 2010.
  11. J. F. Chen, C. R. Yan, Y. C. Lin, J. J. Fan, S. F. Yang, and W. C. Shih, "Effect of drift region process on breakdown voltage in high-voltage n-channel MOSFETs," Proc. 27th International Conference on Circuits/Systems, Computer and Communications, Jul. 2012.
  12. C. R. Yan, J. F. Chen, Y. J. Lee, Y. J. Liao, C. Y. Lin, C. Y. Chen, Y. C. Lin, and H. H. Chen, "Charge pumping current characteristics in advanced NAND flash device," Ext. Abs. 2013 International Workshop on Dielectric Thin Films for Future Electron Devices: Science and Technology, pp. 35-36, Nov. 2013.
  13. Y. S. Fing, Y. M. Liu, and J. F. Chen, "Effects of device dimension on reliability of N-LDMOS transistors," Ext. Abs. 6th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials," p. 04pP56, Mar. 2014.
  14. J. F. Chen, Y. M. Liu, Y. H. Chen, H. T. Hsu, C. Y. Chen, and H. P. Hwang, "Dimension effect on characteristics and hot-carrier reliability in high voltage MOSFETs," Ext. Abs. 2015 International Workshop on Dielectric Thin Films for Future Electron Devices: Science and Technology, pp. 31-32, Nov. 2015.
  15. Y. L. Tsai, J. F. Chen, H. T. Hsu, C. Y. Chen, and H. P. Hwang, "Effects of Si recess on device characteristics and hot-carrier reliability in nMOSFETs, " Ext. Abs. 2016 International Electron Devices and Materials Symposium, p. PC-27, Nov. 2016.
  16. C. Y. Chen, J. F. Chen, Y. L. Tsai, H. T. Hsu, and H. P. Hwang, "Effects of Si recess structure on performance and reliability in high voltage n-MOSFETs, " Ext. Abs. 2017 International Conference on Solid State Devices and Materials, pp. 759-760, Sep. 2017.
專利
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其他
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研究計劃
  1. 混合通道方向基板上製作互補式金氧半電晶體與元件分析之研究(I)(2010)
  2. 混合通道方向基板上製作互補式金氧半電晶體與元件分析之研究(II)(2011)
  3. n通道橫向擴散金氧半電晶體改善其崩潰電壓與可靠度之研究(2012)
  4. 氮化鎵高電子移動率電晶體之改善其崩潰電壓與可靠度之研究(I)(2013)
  5. 高電壓金氧半電晶體可靠度之研究 (2014)
  6. 氧化層間隙壁過蝕刻對矽金氧半電晶體其電性與可靠度影響之研究(2016)
  7. 高電壓矽金氧半電晶體其性能與可靠度改善之研究(2017)
  8. 漂移區設計對高電壓金氧半電晶體其電性與可靠度影響之研究(2018)
  9. 改善高電壓金氧半電晶體其崩潰電壓於可靠度之研究(2020)
開授課程
110學年度上學期
110學年度下學期
指導學生
本學年度 實驗室成員
碩士班
蔡昀蒨
潘科竹
蔡旻辰
鄭智誠
已畢業學生
博士
95
吳國銘
96
李佳叡
97
陳翔裕   田昆玄
98
楊道宏
101
嚴進嶸
103
蔡世昌
107
蔡炎霖
110
吳奕廷
碩士
89
何秋田
90
曹志彬   徐碩賢
91
黃信惇   歐育森
92
林洸萬   陳吉智
93
王鴻鈞
94
陳翔裕   田昆玄   魯建廷
95
嚴進嶸   王瑋傑   黃偉晉
96
陳忠陽
97
吳泰慶   郭育禎
98
黃忠彬   陳建佑   王裕迪   葉怜宜   周亮宇
101
馮雅聖   呂宗翰
102
陳子祥   莊竣堡   張鈞博
103
艾登仁   劉育銘
104
蔡瑋鴻   陳昱鴻
105
鄭世安   沈尚鋒   陳俊諺
106
李佑軒   吳宗翰   詹朝景
107
孫名儒   陳俊庭   林世瑄
108
陳怡婷   盧志邦
109
王兆汯   廖進欽   柯柏豪
特殊榮譽
NCKU EE