NCKU EE 教師個人頁面
English Version
吳誠文 講座教授
地址
奇美系館6樓95609室
TEL
+886-6-2757575 ext.62377
實驗室
可靠運算實驗室
(R95608/ext.62400-2835)
學經歷
學歷
1987
加州大學聖塔芭芭拉分校電機與計算機工程博士
1985
加州大學聖塔芭芭拉分校電機與計算機工程碩士
1981
台灣大學電機工程系學士
經歷
2019/8-
國立成功大學電機工程學系教授兼副校長
2019/1-2019/12
工研院顧問(前瞻指導委員會委員)
2018/1-現在
經濟部4G智慧寬頻應用程式專業審查會總召集人
2017/5-2017/10
行政院科技會報首席評議專家室主任
2016/8-現在
清華大學積體電路設計技術研發中心主任
2015-2016
教育部顧問
2014-現在
新竹市台大校友會理事長;台灣省台大校友會理事;台大校友總會理事
2014-2016
台灣精密工程學會理事
2014-2017/5
經濟部4G智慧寬頻應用城市專業審查會總召集人
2014/2-2016/7
清華大學副校長(研究)
2014/2-現在
清華大學清華特聘講座教授
2014/2-現在
工研院資訊與通訊研究所特聘專家
2010/1-2014/1
工研院資訊與通訊研究所所長
2010-2014
智慧電子系統國家型科技計畫規劃委員、顧問
2007/2-2014/1
臺灣半導體產業協會(TSIA)設計委員會主任委員
2007/2-2009/12
臺灣SOC推動聯盟會長
2007/2-2009/12
工研院系統晶片科技中心主任
2006/2-2014/1
清華大學清華講座教授
2006-2007
國科會晶片系統國家型科技計畫領域召集人
2005
教育部顧問室SOC總聯盟召集人
2004/2-2007/1
清華大學電機資訊學院院長
2002-2014
臺灣IC設計學會理事、監事
2006-2008
矽導計畫晶片系統國家型科技計畫分項顧問
2001-2005
矽導計畫晶片系統國家型科技計畫分項召集人
2002-2005
經濟部技審會技審委員
2001-2014
國科會國家晶片系統設計中心(CIC)諮議委員
2001-2004
教育部顧問室EDA聯盟召集人
2000
教育部顧問室EDA聯盟執行祕書
2001-2007
工研院系統晶片中心顧問
2000-2006
IEEE Taipei Section理事
2000/8-2003/7
清華大學電機系主任
2000/10-2005/1
清華大學積體電路設計技術研發中心主任
1998/3-1999/7
清華大學技術服務中心主任
1996/2-1998/2
清華大學計算機中心主任
1994/8-現在
清華大學電機系教授
1994-1995
工研院電通所設計自動化發展部顧問
1991-1992
交通部電信研究所顧問
1988/3-1994/7
清華大學電機系副教授
1983-1984
行政院衛生署環境保護局技士(系統程式設計)
1983
教育部公費留考 資訊工程學門 第一名
1982
高考電機技師及格
1981-1983
海軍通信電子學校少尉教官
研究領域
  • Design and test of VLSI circuits and systems
  • Semiconductor memory test and repair
  • Symbiotic neuromorphic computing for IOT
著作
期刊論文( Journal )
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  1. H.-H. Liu, B.-Y. Lin, C.-W. Wu, W.-T. Chiang, M. Lee, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “A built-off self-repair scheme for channel-based 3D memories”, IEEE Trans. on Computers, vol. 66, no. 8, pp. 1293-1301, Aug. 2017.
  2. K.-L. Wang, B.-Y. Lin, C.-W. Wu, M. Lee, H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Test cost reduction methodology for InFO wafer-level chip-scale package”IEEE Design & Test, vol. 34, no. 3, pp. 50-58, June 2017.
  3. Z.-Y. Liu, H.-C. Shih, B.-Y. Lin, and C.-W. Wu, “Controller architecture for low-power, low-latency DRAM with built-in cache”, IEEE Design & Test, vol. 34, no. 2, pp. 69~78, Apr. 2017.
  4. B.-Y. Lin, C.-W. Wu, M. Lee, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “A Local Parallel Search Approach for Memory Failure Pattern Identification”, IEEE Trans. on Computers, vol. 65, no. 3, pp. 770~780, Mar. 2016.
  5. B.-Y. Lin, W.-T. Chiang, C.-W. Wu, M. Lee, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Configurable cubical redundancy schemes for channel-based 3D DRAM yield improvement”,IEEE Design & Test, vol. 33, no. 2, pp. 30~39, Mar.-Apr. 2016.
  6. C.-Y. Chen, H.-C. Shih, C.-W. Wu, C.-H. Lin, P.-F. Chiu, S.-S. Sheu, and F. T. Chen, “RRAM defect modeling and failure analysis based on March test and a novel squeeze-search scheme”, IEEE Trans. on Computers, vol. 64, no. 1, pp. 180~189, Jan. 2015.
  7. C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Low-cost post-bond testing of 3D-ICs containing a passive silicon interposer base”, IEEE Trans. on VLSI Systems, vol. 22, no. 11, pp. 2388~2401, Nov. 2014.
  8. H.-C. Shih, P.-W. Luo, J.-C. Yeh, S.-Y. Lin, D.-M. Kwai, S.-L. Lu, A. Schaefer, and C.-W. Wu, "DArT: a component-based DRAM area, power, and timing modeling tool",
  9. C.-C. Chi, B.-Y. Lin, C.-W. Wu, M.-J. Wang, H.-C. Lin, and C.-N. Peng, "On improving interconnect defect diagnosis resolution and yield for interposer-based 3-D ICs",
  10. Y.-L. Peng, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "Application-independent testing of 3-D field programmable gate array interconnect faults",
  11. Y.-F. Chou, D.-M. Kwai, M.-D. Shieh, and C.-W. Wu "Reactivation of spares for off-chip memory repair after die stacking in a 3-D IC with TSVs",
  12. C.-Y. Chen, S.-H. Wang, and C.-W. Wu "Write current self-configuration scheme for MRAM yield improvement",
  13. P.-Y. Chen, C.-L. Su, C.-H. Chen, and C.-W. Wu, “Generalization of an enhanced ECC methodology for low power PSRAM”, IEEE Trans. on Computers, vol. 62, no. 7, pp. 1318~1331, July 2013.
  14. J.-W. You, S.-Y. Huang, Y.-H. Lin, M.-H. Tsai, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu “In-situ method for TSV delay testing and characterization using input sensitivity analysis”, IEEE Trans. on VLSI Systems, vol.21, no.3, pp.443~453, Mar 2013.
  15. H.-M. Sherman Chang, J.-L. Huang, D.-M. Kwai, K.-T. Tim Cheng, and C.-W. Wu, “Low-cost error tolerance scheme for 3-D CMOS imagers”, IEEE Trans. on VLSI Systems, vol.21, no.3, pp.465~474, Mar 2013.
  16. C.-F. Li, C.-Y. Lee, C.-H. Wang, S.-L Chang, L.-M. Denq, C.-C. Chi, H.-J. Hsu, M.-Y. Chu, J.-J. Liou, S.-Y. Huang, P.-C. Huang, H.-P. Ma, J.-C. Bor, C.-W. Wu, C.-C. Tien, C.-H. Wang, Y.-S. Kuo, C.-T. Huang, and T.-Y. Chang, “AC-Plus scan methodology for small delay testing and characterization”, IEEE Trans. on VLSI Systems, vol.21, no. 2, pp.329~341, Feb. 2013.
  17. C.-L. Su, R.-F. Huang, C.-W. Wu, K.-L. Luo, and W.-C. Wu, “A built-in self-diagnosis and repair design with fail pattern identification for memories”, IEEE Trans. on VLSI Systems, vol.19, no.12, pp. 2184~2194, Dec. 2011.
  18. Y.-F. Chou, D.-M. Kwai, and C.-W. Wu, "Yield enhancement by bad-die recycling and stacking with though-silicon vias",
  19. S.-K. Lu, S.-Y. Huang, C.-W. Wu, and Y.-M. Chen, "Speeding up emulation based diagnosis techniques for logic cores",
  20. M. Lee, L.-M. Denq, and C.-W. Wu, "A memory built-in self-repair scheme based on configurable spares",
  21. C.-L. Su, C.-W. Tsai, C.-Y. Chen, W.-Y. Lo, C.-W. Wu, J.-J. Chen, W.-C. Wu, C.-C. Hung, and M.-J. Kao, "Diagnosis of MRAM write disturbance fault",
  22. C.-Y. Lo, Y.-T. Hsing, L.-M. Denq, and C.-W. Wu, "SOC test architecture and method for 3D ICs",
  23. C.-L. Su, R.-F. Huang, C.-W. Wu, K.-L. Luo, and W.-C. Wu, " A built-in self-diagnosis and repair design with fail pattern identification for memories",
  24. Y.-Y. Hsiao, C.-H. Chen, and C.-W. Wu, "Built-in self-repair schemes for flash memories",
  25. Y.-T. Hsing, L.-M. Denq, C.-H. Chen, and C.-W. Wu, "Economic analysis of the HOY wireless test methodology",
  26. M.-Y. Wang and C.-W. Wu, "A mesh-structured scalable IPsec processor”, IEEE Trans. on VLSI Systems, vol. 18, no. 5, pp. 725~731, May 2010.
  27. C.-H. Wang, C.-L. Chuang, and C.-W. Wu, "An efficient multi-mode multiplier supporting AES and fundamental operations of public-key cryptosystems”, IEEE Trans. on VLSI Systems, vol. 18, no. 4, pp. 553~563, Apr. 2010.
  28. M.-Y. Wang, C.-P. Su, C.-L. Horng, C.-W. Wu, and C.-T. Huang, "Single- and multi-core configurable AES architectures for flexible security”, IEEE Trans. on VLSI Systems, vol. 18, no. 4, pp. 541~552, Apr. 2010.
  29. S.-K. Lu, C.-L. Yang, Y.-C. Hsiao, and C.-W. Wu, "Efficient BISR techniques for embedded memories considering cluster faults,"
  30. L.-M. Denq, Y.-T. Hsing, and C.-W. Wu, "Hybrid BIST scheme for multiple heterogeneous embedded memories",
  31. J.-C. Yeh, S.-F. Kuo, C.-H. Chen, and C.-W. Wu, "A systematic approach to memory test time reduction",
  32. C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, D.-Y. Wang, Y.-J. Lee, and M.-J. Kao, "Write disturbance modeling and testing for MRAM",
  33. Y.-L. Peng, J.-J. Liou, C.-T. Huang, and C.-W. Wu, "BIST-based diagnosis scheme for FPGA interconnect delay faults",
  34. R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, “RAISIN: Redundancy analysis algorithm simulation,” IEEE Design & Test of Computers, vol. 24, no. 4, pp. 386~396, Jul.-Aug. 2007.
  35. J.-C. Yeh, K.-L. Cheng, Y.-F. Chou, and C.-W. Wu, "Flash memory testing and built-in self-diagnosis with march-like test algorithms",
  36. C.-Y. Lo, C.-H. Wang, K.-L. Cheng, J.-R. Huang, C.-W. Wang, S.-M. Wang, and C.-W. Wu, "STEAC: A platform for automatic SOC test integration",
  37. R.-F. Huang, C.-H. Chen, and C.-W. Wu, "Economic aspects of memory built-in self-repair",
  38. S.-K. Lu, Y.-C. Tsai, C.-H. Hsu, K.-H. Wang, and C.-W. Wu, "Efficient built-in redundancy analysis for embedded memories with 2-D redundancy",
  39. J.-F. Li, J.-C. Yeh, R.-F. Huang, and C.-W. Wu, "A built-in self-repair design for RAMs with 2-D redundancy",
  40. H.-C. Hong and C.-W. Wu, "Selection of high-order analog response extractor for S-∆ modulation based analog built-in self-test applications", Int. Jour. of Electrical Engineering, vol. 11, no. 2, pp. 103~115, May 2004.
  41. C.-P. Su and C.-W. Wu, "A graph-based approach to power-constrained SOC test scheduling",
  42. B.-H. Lin, C.-W. Wu, and H.-T. A. Luh, "Efficient and economic test equipment setup by pro-correlation",
  43. C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, "A high-throughput low-cost AES processor",
  44. J.-H. Hong and C.-W. Wu, "Cellular array modular multiplier for the RSA public-key cryptosystem based on modified Booth's algorithm",
  45. H.-C. Kao, M.-F. Tsai, S.-Y. Huang, C.-W. Wu, W.-F. Chang, and S.-K. Lu, "Efficient double fault diagnosis for CMOS logic circuits with a specific application to generic bridging faults",
  46. C.-T. Huang, C.-F. Wu, J.-F. Li, and C.-W. Wu, "Built-in redundancy analysis for memory yield improvement",
  47. H.-C. Hong, J.-L Huang, K.-T. Cheng, C.-W. Wu, and D.-M. Kwai, "Practical considerations in applying S-∆ modulation-based analog BIST to sampled-data systems", IEEE Trans. On Circuits and Systems II: Analog and Digital Signal Processing, vol. 50, no. 9, pp. 553-566, Sept. 2003.
  48. S.-H. Shieh and C.-W. Wu, "Asymmetric high-radix signed-digit number systems for carry-free addition",
  49. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Testing and diagnosis methodologies for embedded content addressable memories",
  50. K.-L. Cheng, M.-F. Tsai, and C.-W. Wu, "Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories",
  51. J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "A hierarchical test methodology for system-on-chip",
  52. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Diagnostic data compression techniques for embedded memories with built-in self-test",
  53. C.-F. Wu, C.-T. Huang, K.-L. Cheng, and C.-W. Wu, "Fault simulation and test algorithm generation for random access memories",
  54. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, "A built-in self-test and self-diagnosis scheme for embedded SRAM",
  55. J.-F. Li and C.-W. Wu, "Efficient FFT network testing and diagnosis schemes",
  56. C.-H. Wu, J.-H. Hong, and C.-W. Wu, "VLSI design of RSA cryptosystem based on the Chinese Remainder Theorem",
  57. C.-W. Wu, J.-F. Li, and C.-T. Huang, "Core-based system-on-chip testing: Challenges and opportunities",
  58. S.-A. Hwang and C.-W. Wu, "Unified VLSI systolic array design for LZ data compression",
  59. K.-J. Lin and C.-W. Wu, "A low-power CAM design for LZ data compression",
  60. C.-F. Wu and C.-W. Wu, "Testing and diagnosing dynamic reconfigurable FPGA",
  61. B.-H. Lin, S.-H. Shieh, and C.-W. Wu, "A fast signature computation algorithm for LFSR and MISR",
  62. J.-F. Li, S.-K. Lu, S.-A. Hwang, and C.-W. Wu, "Easily testable and fault tolerant FFT buttery networks",
  63. C.-T. Huang and C.-W. Wu, "High-speed easily testable Galois field inverter",
  64. C.-Y. Su and C.-W. Wu, "A probabilistic model for path delay fault testing",
  65. K.-J. Lin and C.-W. Wu, "Testing content-addressable memories using functional fault models and March-like algorithms",
  66. J.-H. Hong, C.-H. Tsai, and C.-W. Wu, "Hierarchical system test by an IEEE 1149.5 MTM-Bus slave-module interface core",
  67. S.-A. Hwang and C.-W. Wu, "Test energy minimization for C-testable ILAs",
  68. W.-F. Chang and C.-W. Wu, "Low-cost modular totally self-checking checker design for m-out-of-n code",
  69. C.-Y. Su, S.-A. Hwang, P.-S. Chen, and C.-W. Wu, "An improved Montgomery algorithm for high-speed RSA public-key cryptosystem",
  70. W.-F. Chang and C.-W. Wu, "TSC Berger code checker design for 2r-1-bit information",
  71. C.-T. Huang, J.-R. Huang, C.-F. Wu, C.-W. Wu, and T.-Y. Chang, "A programmable BIST core for embedded DRAM",
  72. S.-A. Hwang, J.-H. Hong, and C.-W. Wu, "Sequential circuit fault simulation using logic emulation",
  73. Y.-R. Shieh and C.-W. Wu, "Control and observation structures for analog circuits",
  74. Y.-R. Shieh and C.-W. Wu, "Design of CMOS PSCD circuits and checkers for stuck-at and stuck-on faults",
  75. W.-F. Chang and C.-W. Wu, "Does there exist a combinational TSC checker for 1/3 code using only primitive gates?",
  76. S.-K. Lu, S.-Y. Kuo, and C.-W. Wu, "Fault-tolerant interleaved memory systems with tow-level redundancy",
  77. Y.-L. Li, Y.-C. Lai, and C.-W. Wu, "VLSI design of a cellular-automata based logic and fault simulator",
  78. K.-J. Lin and C.-W. Wu, "Practical realization of multiple-input exclusive-OR circuits for low-power applications",
  79. S.-K. Lu, C.-W. Wu, and R.-Z. Hwang, "Cell delay fault testing for iterative logic arrays",
  80. C.-W. Wu and M.-K. Chang, "Bit-level systolic arrays for finite-field multiplications",
  81. Y.-L. Li and C.-W. Wu, "Cellular automata for efficient parallel logic and fault simulation",
  82. S.-K. Lu, J.-C. Wang, and C.-W. Wu, "C-testable design techniques for iterative logic arrays",
  83. C.-Y. Su and C.-W. Wu, "Testing iterative logic arrays for sequential faults with a constant number of patterns",
  84. S.-K. Lu, C.-W. Wu, and S.-Y. Kuo, "Enhancing testability of VLSI arrays for fast Fourier transform",
  85. C.-W. Wu and J.-Y. Choue, "Fault tolerant FFT buttery network design",
  86. C.-W. Wu and C.-T. Chang, "FFT buttery network design for easy testing",
  87. K.-J. Lin and C.-W. Wu, "Realization of pipelined mesh algorithms on hypercubes",
  88. C.-W. Wu, S.-F. Shu, and K.-J. Lin, "Automatic synthesis of testable VLSI cellular array multipliers",
  89. K.-J. Lin and C.-W. Wu, "Easily testable cellular array multipliers",
  90. C.-W. Wu, "Bit-level pipelined 2-D digital filters for real-time image processing",
  91. C.-W. Wu and P. R. Cappello, "Easily testable iterative logic arrays",
  92. C.-W. Wu, "Relating tiling and coloring to testing of combinational iterative logic arrays",
  93. C.-W. Wu and P. R. Cappello, "Block multipliers unify bit-level cellular multiplications",
  94. C.-W. Wu and P. R. Cappello, "Application specific CAD of VLSI second-order sections",
  95. P. R. Cappello and C.-W. Wu, "Computer-aided design of VLSI FIR filters",
會議論文( Conference )
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  1. E. J. Marinissen, F. Fodor, A. Podpod, M. Stucchi, Y.-R. Jian, and C.-W. Wu, “Solutions to Multiple Probing Challenges for Test Access to Multi-Die Stacked Integrated Circuits,” in Proc. IEEE Int. Test Conf. (ITC), Phoenix, Oct. 2018 (to appear).
  2. Y.-C. Kao and C.-W. Wu, "A Self-Organizing Map-Based Adaptive Traffic Light Control System with Reinforcement Learning", in Proc. IEEE 52nd
  3. M.-C. Chen, T.-H. Wu, and C.-W. Wu, “A Built-in Self-Test Scheme for Detecting Defects in FinFET-Based SRAM Circuit,” in Proc. 27th IEEE Asian Test Symp. (ATS), Hefei, Aug. 2018 (to appear).
  4. J.-Y. Hu, K.-W. Hou, C.-Y. Lo, Y.-F. Chou, and C.-W. Wu, “RRAM-Based Neuromorphic Hardware Reliability Improvement by Self-Healing and Error Correction,” in Proc. IEEE Int. Test Conf. in Asia (ITC-A), Harbin, Aug. 2018 (to appear).
  5. Y.-C. Pan, Y.-R. Jian, H.-H. Liu, and C.-W. Wu, "A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices," in Proc. VLSI Test Technology Workshop (VTTW), Nantou, Jul. 2018 (to appear).
  6. S.-F. Kuo and C.-W. Wu, “Symbiotic Controller Design Using a Memory-Based FSM Model,” in Proc. Int. Symp. Industrial Electronics (ISIE), Cairns, June 2018.
  7. Y.-R. Jian, F. Fodor, E. J. Marinissen, and C.-W. Wu, “Automated Probe Mark Analysis,” in Semiconductor Wafer Test Workshop (SWTW), San Diego, June 2018.
  8.  P.-Y. Chuang, C.-W. Wu, and H. H. Chen, “Covering Hard-to-Detect Defects by Thermal Quorum Sensing,” in Proc. IEEE European Test Symposium (ETS), Bremen, May 2018.
  9. P.-M. P. Law, C.-W. Wu, L.-Y. Lin, H.-C. Hong, H. Chen, H.-C. Lin, and M.-J. Wang, "An Enhanced Boundary Scan Architecture for Inter-Die Interconnect Leakage Measurement in 2.5D and 3D Packages," in Proc. 26th
  10. B.-Y. Lin, H.-W. Hung, S.-M. Tseng, C. Chen, and C.-W. Wu, “Highly Reliable and Low-Cost Symbiotic IOT Devices and Systems,” in Proc. IEEE Int. Test Conf. (ITC), Fort Worth, Texas, Oct. 2017. (Invited)
  11.  C.-W. Wu, B.-Y. Lin, H.-W. Hung, S.-M. Tseng, and C. Chen, “Symbiotic System Models for Efficient IOT System Design and Test,” in Proc. IEEE Int. Test Conf. in Asia (ITC-A), Taipei, Sept. 2017.
  12.  P.-Y. Chuang, C.-W. Wu, and H. H. Chen, “Cell-Aware Test Generation Time Reduction by Using Switch-Level ATPG,” in Proc. IEEE Int. Test Conf. in Asia (ITC-A), Taipei, Sept. 2017.
  13. K.-W. Hou and C.-W. Wu, "Fault Models and Test Algorithms for Multi-Level Cell (MLC) Crossbar RRAM," in Proc. VLSI Test Technology Workshop (VTTW), Nantou, Jul. 2017.
  14. H. H. Chen, S. Chen, P.-Y. Chuang, and C.-W. Wu, "Efficient Cell-Aware Fault Modeling by Switch-Level Test Generation," in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016. (Best Paper Award)
  15. H.-W. Liu and C.-W. Wu, "Layout-Oriented Defect Set Reduction for Fast Circuit Simulation in Cell-Aware Test," in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016.
  16. Y.-C. Huang, B.-Y. Lin, C.-W. Wu, M. Lee, H. Chen, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Efficient probing schemes for fine-pitch pads of InFO wafer-level chip-scale package”, in Proc. IEEE/ACM Design Automation Conf. (DAC), Austin, USA, June 2016.
  17. S.-Y. Wei, B.-Y. Lin, and C.-W. Wu, “A fast sweep-line-based failure pattern extractor for memory diagnosis,” in Proc. IEEE Eropean Test Symposium (ETS), Amsterdam, May 2016.
  18.  P.-W. Luo, C.-K. Chen, Y.-H. Sung, W. Wu, H.-C. Shih, C.-H. Lee, K.-H. Lee, M.-W. Li, M.-C. Lung, C.-N. Lu, Y.-F. Chou, P.-L. Shih, C.-H. Ke, C. Shiah, P. Stolt, S. Tomishima, D.-M. Kwai, B.-D. Rong, N. Lu, S.-L. Lu, and C.-W. Wu, “A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs,” in Proc. IEEE Symp. VLSI Circuits (VLSI), June 2015.
  19. B.-Y. Lin, C.-W. Wu, and H. H. Chen, “System-level test coverage prediction by structural stress test data mining,” in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2015.
  20. Y.-C. Yu, C.-C. Yang, J.-F. Li, C.-Y. Lo, C.-H. Chen, J.-S. Lai, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, "BIST-assisted tuning scheme for minimizing IO-channel power of TSV-based 3D DRAMs," in Proc. 23rd IEEE Asian Test Symp. (ATS), Hangzhou, Nov. 2014.
  21.  B.-Y. Lin, W.-T. Chiang, C.-W. Wu, M. Lee, H.-C. Lin, C.-N. Peng, and M.-J. Wang, “Redundancy architectures for channel-based 3D DRAM yield improvement,” in Proc. IEEE Int. Test Conf. (ITC), Seattle, Washington, Oct. 2014.
  22. B.-Y. Lin, M. Lee, and C.-W. Wu, "Exploration methodology for 3D memory redundancy architectures under redundancy constraints," in Proc. 22nd IEEE Asian Test Symp. (ATS), Yilan, Nov. 2013.
  23. B.-Y. Lin, M. Lee, C.-W. Wu, "Failure-Pattern-Based Test Data Compression for Memories," in Proc. VLSI Test Technology Workshop (VTTW), New Taipei City, Jul. 2013.
  24. Y.-C. Yu, C.-S. Hou, L.-J. Chang, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu “A hybrid ECC and redundancy technique for reducing refresh power of DRAMs”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013.
  25.  C.-S. Hou, J.-F. Li, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou , and C.-W. Wu “An FPGA-Based Test Platform for Analyzing Data Retention Time Distribution of DRAMs”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013.
  26. C.-C. Chi, C.-W. Wu, M.-J. Wang, and H.-C. Lin, “3D-IC Interconnect Test, Diagnosis, and Repair”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013.
  27. Y. Shiyanovskii, C. Papachristou, and C.-W. Wu, “Analytical modeling and numerical simulations of temperature field in TSV-based 3D ICs”, in Proc. 14th Int. Symp. on Quality Electronic Design (ISQED), Santa Clara, CA, Mar. 2013.
  28. H.-C. Shih, and C.-W. Wu, "An enhanced double-TSV scheme for defect tolerance in 3D-IC", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Grenoble, Mar. 2013.
  29. S.-S. Chen, C.-K. Hsu, H.-C. Shih, J.-C. Yeh, C.-W. Wu, “Processor and DRAM integration by TSV-based 3-D stacking for power-aware SOCs”, in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2013.
  30. Y.-C. Yu, J.-F. Li, C.-W. Chou, C.-Y. Lo, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A built-in self-test scheme for 3-D RAMs”, in Proc. IEEE Int. Test Conf. (ITC), Anaheim, CA, Nov. 2012, Paper 14.4.
  31. T.-H. Wu, P.-Y. Chen, M. Lee, B.-Y. Lin, C.-W. Wu, C.-H. Tien, H.-C. Lin, H. Chen, C.-N. Peng, and M.-J. Wang, “A memory yield improvement scheme combining built-in self-repair and error correction codes”, in Proc. IEEE Int. Test Conf. (ITC), Anaheim, CA, Nov. 2012, Paper 14.1.
  32.  C.-C. Chi, Y.-F. Chou. D.-M. Kwai, Y.-Y. Hsiao, C.-W. Wu, Y.-T. Hsing, L.-M. Denq, and T.-H. Lin, “3D-IC BISR for stacked memories using cross-die spares”, in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2012, pp. 1-4.
  33. Y.-W. Chou, P.-Y. Chen, M. Lee, and C.-W. Wu, “Cost modeling and analysis for interposer-based three-dimensional IC”, in Proc. 29th IEEE VLSI Test Symp. (VTS), Maui, Hawaii, Apr. 2012, pp. 108-113.
  34. B.-Y. Lin, M. Lee and C.-W. Wu, “A memory failure pattern analyzer for memory diagnosis and repair”, in Proc. 29th IEEE VLSI Test Symp. (VTS), Maui, Hawaii, Apr. 2012, pp. 234-239.
  35. C.-W. Wu, S.-K. Lu, and J.-F. Li, “On test and repair of 3D random access memory”, in Proc. 17th Asia and South Pacific Design Automation Conference (ASP-DAC), Sydney, Australia, Jan. 2012, pp. 744-749.
  36. C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Multi-visit TAMs to reduce the post-bond test length of 2.5D-SICs with a passive silicon interposer base”, in Proc. 20th IEEE Asian Test Symp. (ATS), New Delhi, India, Nov. 2011, pp. 451-456.
  37. C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base”, in Proc. IEEE Int. Test Conf. (ITC), Anaheim, USA, Sept. 2011, Paper 17.3.
  38. C.-Y. Chen, H.-C. Shih, M. Lee, C.-W. Wu, C.-H. Lin, and S.-S. Sheu, “Built-in self-forming, built-in self-test, and built-in self-repair for RRAM yield improvement,” in Proc. VLSI Test Tech. Workshop (VTTW), Nantou, July 2011.
  39. C.-F. Li, C.-Y. Lee, C.-H. Wang, S.-L. Chang, Y.-S. Kuo, L.-M. Denq, C.-C. Chi, T.-Y. Chang, H.-J. Hsu, M.-Y. Chu, C.-T. Huang, J.-J. Liou, S.-Y. Huang, P.-C. Huang, H.-P. Ma, J.-C. Bor, C.-C. Tien, C.-H. Wang, and C.-W. Wu, “A low-cost wireless interface with no external antenna and crystal oscillator for cm-range contactless testing”, in Proc. IEEE/ACM Design Automation Conf. (DAC), San Diego, USA, June 2011, pp. 771-776
  40. C.-C. Chi, E. J. Marinissen, S. K. Goel, and C.-W. Wu, “DfT architecture for 3D-SICs with multiple towers”, in Proc. 16th IEEE European Test Symp. (ETS), Trondheim, Norway, May 2011, pp. 51-56.
  41. Y.-J. Huang, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A built-in self-test scheme for the post-bond test of TSVs in 3D ICs”, in Proc. 28th IEEE VLSI Test Symp. (VTS), Dana Point, May 2011, pp. 20~25.
  42. H.-C. Shih, C.-Y. Chen, C.-W. Wu, C.-H. Lin, and S.-S. Sheu, “Training-based forming process for RRAM yield improvement”, in Proc. 28th IEEE VLSI Test Symp. (VTS), Dana Point, May 2011, pp. 146~151.
  43. X.-L. Huang, P.-Y. Kang, H.-M. Chang, J.-L. Huang, Y.-F. Chou, Y.-P. Lee, D.-M. Kwai, and C.-W. Wu, “A self-testing and calibration method for embedded successive approximation register ADC”, in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Japan, Jan. 2011, pp. 713-718.
  44. C.-W. Chou, J.-F. Li, J.-J. Chen, D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “A test integration methodology for 3D integrated circuits,” in Proc. 19th IEEE Asian Test Symp. (ATS), Shanghai, Dec. 2010, pp. 377~382.
  45. , and C.-W. Wu, “Performance characterization of TSV in 3D IC via sensitivity analysis,” in Proc. 19th IEEE Asian Test Symp. (ATS), Shanghai, Dec. 2010, pp. 389~394.
  46. D.-M. Kwai, Y.-F. Chou, and C.-W. Wu, “Is 3D integration the way out of the crossroads?” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Beijing, Nov. 2010, pp. 1~4.
  47. T.-Y. Lee, S.-Y. Huang, H.-J. Hsu, C.-W. Tzeng, C.-T. Huang, J.-J. Liu, H.-P. Ma, P.-C. Huang, J.-C. Bor, C.-W. Wu, C.-C. Tien, M. Wang, "AF-Test: Adaptive-frequency scan test methodology for small-delay defects", in Proc. IEEE 25th Int. Symp. Defect and Fault Tolerance in VLSI Systems (DFT), Oct. 2010, pp. 340~348.
  48. C.-W. Wu and J.-J. Tang, “Is automotive electronics creating new opportunities for semiconductor?” in Proc. 16th Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), Taipei, Oct. 2010.
  49. H.-M. Chang, J.-L. Huang, D.-M. Kwai, K.-T. Tim Cheng, and C.-W. Wu, "An error tolerance scheme for 3D CMOS imagers", in Proc. IEEE/ACM Design Automation Conf. (DAC), Anaheim, June 2010, pp. 917~922.
  50. S.-H. Wang, C.-Y. Chen, and C.-W. Wu, "Fast identification of operating current for Toggle MRAM by spiral search", in Proc. IEEE/ACM Design Automation Conf. (DAC), Anaheim, June 2010, pp. 923~928.
  51. C.-C. Chi, C.-W. Wu, and J.-F. Li, “A low-cost and scalable test architecture for multi-core chips”, in Proc. IEEE European Test Symp. (ETS), May 2010, pp. 30~35.
  52. T.-Y. Wu, P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, "Improving testing and diagnosis efficiency for regular memory arrays", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2010, pp. 100~103.
  53. P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-chip testing of blind-via and open-sleeve TSVs for 3D IC before bonding”, in Proc. 28th IEEE VLSI Test Symp. (VTS), Santa Cruz, Apr. 2010, pp. 263~268.
  54. C.-Y. Chen and C.-W. Wu, "An adaptive code rate EDAC scheme for 16-bit random access memory," in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Dresden, Mar. 2010, pp. 735~740.
  55. J.-F. Li and C.-W. Wu, “Is 3D integration an opportunity or just a hype?” in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Taipei, Jan. 2010, pp. 541~543.
  56. P.-Y. Chen, C.-W. Wu, and D.-M. Kwai, “On-chip TSV testing for 3D IC before bonding using sense amplification,” in Proc. 18th IEEE Asian Test Symp. (ATS), Taichung, Nov. 2009, pp. 450~455.
  57. C.-C. Chi, C.-Y. Lo, T.-W. Ko, and C.-W. Wu, “Test integration for SOC supporting very low cost testers”, in Proc. 18th IEEE Asian Test Symp. (ATS), Taichung, Nov. 2009, pp. 287~292.
  58. Y.-F. Chou, D.-M. Kwai, and C.-W. Wu, “Memory repair by die stacking with through-silicon vias,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Aug. 2009, pp. 53~58.
  59. Y.-L. Peng and C.-W. Wu, “Testing for 3D FPGA interconnect open and short faults,” in Proc. 3rd VLSI Test Technology Workshop (VTTW), Nantou, July 2009.
  60.  T.-H. Chen, Y.-Y. Hsiao, Y.-T. Hsing, and C.-W. Wu, “An Adaptive-Rate Error Correction Scheme for NAND Flash Memory Regular Papers”, in Proc. 27th IEEE VLSI Test Symp. (VTS), Santa Cruz, May 2009, pp. 53~58.
  61. C.-W. Tzeng, C.-Y. Lin, S.-Y. Huang, C.-T. Huang, J.-J. Liou, H.-P. Ma, P.-C. Huang, and C.-W. Wu, "iScan: Indirect-access scan test over HOY test platform", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2009, pp. 60~63.
  62. W.-Y. Lo, C.-Y. Chen, C.-L. Su, and C.-W. Wu, "Test and diagnosis algorithm generation and evaluation for MRAM Write Disturbance Fault", in Proc. 17th IEEE Asian Test Symp. (ATS), Sapporo, Japan, Nov. 2008, pp. 417~422.
  63. C.-H. Lin, M.-S. Lee, C.-L. Su, and C.-W. Wu, “Evaluation of Redundancy Analysis Schemes for Reparable Memories with Redundancy Constraints”, in Proc. 2nd VLSI Test Technology Workshop (VTTW), Tainan, July 2008.
  64. Y.-T. Hsing, S.-G. Wu, and C.-W. Wu, “RAMSES-D: DRAM fault simulator supporting weighted coupling fault,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Dec. 2007, pp. 33~38.
  65. H.-H. Wu, J.-F. Li, C.-F. Wu, and C.-W. Wu, “CAMEL: An efficient fault simulator with coupling fault simulation enhancement for CAMs,” in Proc. 16th IEEE Asian Test Symp. (ATS), Beijing, Oct. 2007, pp. 355~360.
  66. L.-M. Denq and C.-W. Wu, “A hybrid BIST scheme for multiple heterogeneous embedded memories”, in Proc. 16th IEEE Asian Test Symp. (ATS), Beijing, Oct. 2007 , pp. 349~354.
  67. C.-L. Su, C.-W. Tsai, C.-W. Wu, J.-J. Chen, W.-C. Wu, C.-C. Hung, and M.-J. Kao, "Diagnosis for MRAM write disturbance fault", in Proc. IEEE Int. Test Conf. (ITC), Santa Clara, Oct. 2007, pp. 1-9.
  68. J.-J. Liou, C.-T. Huang, C.-W. Wu, C.-C. Tien, C.-H. Wang, H.-P. Ma, Y.-Y. Chen, Y.-C. Hsu, L.-M. Deng, C.-J. Chiu, Y.-W. Li, and C.-M. Chang, “A prototype of a wireless-based test system,” in Proc. IEEE Int. SOC Conf. (SOCC), Sept. 2007, pp. 225~228.
  69. C.-W. Wu, “How far can we go in wireless testing of memory chips and wafers?,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Dec. 2007, pp. 31~32.
  70. Y.-T. Hsing, S.-G. Wu, and C.-W. Wu, “RAMSES-D: DRAM fault simulator supporting weighted coupling fault,” in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Dec. 2007, pp. 33~38.
  71. W.-Y. Lo, C.-Y. Chen, C.-L. Su, and C.-W. Wu, "Testing MRAM for write disturbance fault", in Proc. 18th VLSI Design/CAD Symp., Hualien, Aug. 2007 (Best Paper Award).
  72. M.-S. Lee and C.-W. Wu, “BRAINS+: A Memory Built-in Self-Repair Generator,” in Proc. 1st VLSI Test Technology Workshop (VTTW), Hsinchu, July 2007.
  73. Y.-T. Hsing, C.-C. Huang, J.-C. Yeh, and C.-W. Wu, "SDRAM delay fault modeling and performance testing", in Proc. 25th IEEE VLSI Test Symp. (VTS), Berkeley, May 2007, pp. 53~58.
  74. T.-W. Ko, Y.-T. Hsing, C.-W. Wu, and C.-T. Huang, "Stable performance MAC protocol for HOY wireless tester under large population", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2007, pp. 160~163.
  75. L.-M. Denq, T.-C. Wang, and C.-W. Wu, "An enhanced SRAM BISR design with reduced timing penalty", in Proc. 15th IEEE Asian Test Symp. (ATS), Fukuoka, Japan, Nov. 2006, pp. 25~30.
  76. B.-Y. Chen, Y.-T. Yeh, C.-H. Chen, J.-C. Yeh, C.-W. Wu, J.-S. Lee, and Y.-C. Lin, "An enhanced EDAC methodology for low power PSRAM", in Proc. IEEE Int. Test Conf. (ITC), Santa Clara, Oct. 2006.
  77. C.-L. Su, C.-W. Tsai, C.-W. Wu, C.-C. Hung, Y.-S. Chen, and M.-J. Kao, "Testing MRAM for write disturbance fault", in Proc. IEEE Int. Test Conf. (ITC), Santa Clara, Oct. 2006.
  78. M.-H. Hsu, Y.-T. Hsing, J.-C. Yeh, and C.-W. Wu, "Fault-pattern oriented defect diagnosis for flash memory", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Aug. 2006, pp. 3~8.
  79. C.-H. Wang, C.-Y. Lo, M.-S. Lee, J.-C. Yeh, C.-T. Huang, C.-W. Wu, and S.-Y. Huang, "A network security processor design based on an integrated SOC design and test platform", in Proc. IEEE/ACM Design Automation Conf. (DAC), San Francisco, July 2006.
  80. Y.-Y. Hsiao, C.-H. Chen, and C.-W. Wu, "A built-in self-repair scheme for NOR-type flash memory", in Proc. IEEE VLSI Test Symp. (VTS), Berkeley, Apr. 2006, pp. 114~119.
  81. P.-K. Chen, Y.-T. Hsing, and C.-W.Wu, "On feasibility of HOY-a wireless test methodology for VLSI chips and wafers", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006, pp. 243~246.
  82. C.-W. Wu, C.-T. Huang, S.-Y. Huang, P.-C. Huang, T.-Y. Chang, and Y.-T. Hsing, "The HOY tester-Can IC testing go wireless?", in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2006, pp. 183~186.
  83. Y.-C. Dawn, J.-C. Yeh, C.-W. Wu, C.-C. Wang, Y.-C. Lin, and C.-H. Chen, "Flash memory die sort by a sample classi_cation method", in Proc. 14th IEEE Asian Test Symp. (ATS), Kolkatta, India, Dec. 2005, pp. 182~187.
  84. C.-H. Wang, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, "Scalable security processor design and its implementation", in Proc. IEEE Asian Solid-State Circuit Conf. (A-SSCC), Hsinchu, Nov. 2005, pp. 513~516.
  85. C.-L. Su, Y.-T. Yeh, and C.-W. Wu, "An integrated ECC and redundancy repair scheme for memory reliability enhancement", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Monterey, CA, Oct. 2005, pp. 81~89.
  86. C.-K. Tung, S.-H. Shieh, M.-C. Tsai, and C.-W. Wu, "Novel hybrid full-swing full adder cores with output driving capability", in Proc. 16th VLSI Design/CAD Symp., Hualien, Aug. 2005.
  87. S.-M. Wang, C.-Y. Lo, C.-H. Wang, and C.-W. Wu, "Test integration of core-based system-on-chip supporting delay test", in Proc. 16th VLSI Design/CAD Symp., Hualien, Aug. 2005.
  88. J.-C. Yeh, S.-F. Kuo, C.-W. Wu, C.-T. Huang, and C.-H. Chen, "A systematic approach to reducing semiconductor memory test time in mass production", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Taipei, Aug. 2005, pp. 97~102.
  89. C.-C. Wang, J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu, "A BIST scheme for FPGA interconnect delay faults", in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 201~206.
  90. J.-C. Yeh, Y.-T. Lai, Y.-Y. Shih, and C.-W. Wu, "Flash memory built-in self-diagnosis with test mode control", in Proc. IEEE VLSI Test Symp. (VTS), Palm Springs, May 2005, pp. 15~20.
  91. H.-C. Liao, J.-J. Liou, Y.-L. Peng, C.-T. Huang, and C.-W. Wu, "Delay defect coverage for FPGA test configurations based on statistical evaluation", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications: Design, Automation and Test (VLSI-TSA-DAT), Hsinchu, Apr. 2005, pp. 217~220.
  92. C.-L. Su, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and S.-T. Lin, "Embedded memory diagnostic data compression using differential address", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications: Design, Automation and Test (VLSI-TSA-DAT), Hsinchu, Apr.2005, pp. 20~23.
  93. C.-W. Wu, "SOC testing methodology and practice", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Munich, Mar. 2005, pp. 1120~1121.
  94. C.-P. Su, C.-L. Horng, C.-T. Huang, and C.-W. Wu, "A configurable AES processor for enhanced security", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Shanghai, Jan. 2005, pp. 361~366.
  95. H.-C. Hong, C.-W. Wu, and K.-T. Cheng, "A S-∆ modulation based analog BIST system with a wide bandwidth _fth-order analog response extractor for diagnosis purpose", in Proc.13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 62~67.
  96. C.-T. Huang, J.-C. Yeh, Y.-Y. Shih, R.-F. Huang, and C.-W. Wu, "On test and diagnostics of flash memories", in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 260~265.
  97. R.-F. Huang, C.-L. Su, C.-W. Wu, S.-T. Lin, K.-L. Luo, and Y.-J. Chang, "Fail pattern identification for memory built-in self-repair", in Proc. 13th IEEE Asian Test Symp. (ATS), Kenting, Taiwan, Nov. 2004, pp. 366~371.
  98. K.-L. Cheng, J.-R. Huang, C.-W. Wang, C.-Y. Lo, L.-M. Denq, C.-T. Huang, C.-W. Wu, S.-W. Hung, and J.-Y. Lee, "An SOC test integration platform and its industrial realization", in Proc. IEEE Int. Test Conf. (ITC), Charlotte, Oct. 2004, pp. 1213~1222.
  99. C.-L. Su, R.-F. Huang, C.-W. Wu, C.-C. Hung, M.-J. Kao, Y.-J. Chang, and W.-C. Wu, "MRAM defect analysis and fault modeling", in Proc. IEEE Int. Test Conf. (ITC), Charlotte, Oct. 2004, pp. 124~133.
  100. Y.-L. Peng, J.-J. Liou, C.-T. Huang, and C.-W. Wu, "An application-independent delay testing methodology for island-style FPGA", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2004, pp. 478~486.
  101. Y.-T. Hsing, C.-W. Wang, C.-W. Wu, C.-T. Huang, and C.-W. Wu, "Failure factor based yield enhancement for SRAM designs", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Cannes, Oct. 2004, pp. 20~28.
  102. S.-H. Shieh and C.-W. Wu, "A systematic approach to semiconductor memory test time reduction", in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.
  103. Y.-T. Lai, J.-C. Yeh, C.-W.Wu, and C.-H. Ho, "Flash memory built-in self-test with enhanced test mode control", in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.
  104. S.-F. Kuo, J.-C. Yeh, C.-W. Wu, and C.-H. Chen, "A systematic approach to semiconductor memory test time reduction", in Proc. 15th VLSI Design/CAD Symp., Pingtung, Aug. 2004.
  105. C.-H. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "A word-based RSA crypto-processor with enhanced pipeline performance", in Proc. 4th IEEE Asia-Pacific Conf. on Advanced System Integrated Circuits (AP-ASIC), Fukuoka, Aug. 2004, pp. 218~221.
  106. R.-F. Huang, C.-L. Su, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "A memory built-in self- diagnosis design with syndrome compression", in Proc. IEEE Int. Workshop on Current & Defect Based Testing (DBT), Napa Valley, Apr. 2004, pp. 97~102.
  107. R.-F. Huang, Y.-T. Lai, Y.-F. Chou, and C.-W. Wu, "SRAM delay fault modeling and test algorithm development", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP- DAC), Yokohama, Jan. 2004, pp. 104~109.
  108. M.-Y. Wang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "An HMAC processor with integrated SHA-1 and MD5 algorithms", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2004, pp. 456~458.
  109. C.-L. Su, R.-F. Huang, and C.-W. Wu, "A processor-based built-in self-repair design for embedded memories", in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 366~371.
  110. R.-F. Huang, Y.-F. Chou, and C.-W. Wu, "Defect oriented fault analysis for SRAM", in Proc. 12th IEEE Asian Test Symp. (ATS), Xian, Nov. 2003, pp. 256~261.
  111. K.-L. Cheng, C.-W. Wang, J.-N. Lee, Y.-F. Chou, C.-T. Huang, and C.-W. Wu, "FAME: a fault-pattern based memory failure analysis framework", in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2003, pp. 595~598.
  112. J.-F. Li, J.-C. Yeh, R.-F. Huang, C.-W. Wu, P.-Y. Tsai, A. Hsu, and E. Chow, "A built-in self-repair scheme for semiconductor memories with 2-D redundancy", in Proc. IEEE Int. Test Conf. (ITC), Charlotte, Sept. 2003, pp. 393~402.
  113. S.-H. Shieh and C.-W. Wu, "Carry-free adder design based on minimal redundant positive-digit number system", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 257~260.
  114. H.-C. Liao, R.-F. Huang, J.-J. Liou, and C.-W. Wu, "An FPGA fault simulator for stuck-at and segment delay faults", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 461~464.
  115. L.-M. Denq, R.-F. Huang, C.-W. Wu, Y.-J. Chang, and W.-C. Wu, "A parallel built-in self-diagnosis scheme for embedded memory", in Proc. 14th VLSI Design/CAD Symp., Hualien, Aug. 2003, pp. 449~452.
  116. C.-P. Su, T.-F. Lin, C.-T. Huang, and C.-W. Wu, "A highly efficient AES cipher chip", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Kitakyushu, Jan. 2003, pp. 561~562 (Design Contest Special Feature Award).
  117. H.-C. Hong, J.-L. Huang, K.-T. Cheng, and C.-W. Wu, "On-chip analog response extraction with 1-bit sigma-delta modulators", in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 49~54.
  118. H.-S. Hsu, J.-R. Huang, K.-L. Cheng, C.-W. Wang, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "Test scheduling and test access architecture optimization for system-on-chips", in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 411~416.
  119. C.-W. Wang, J.-R. Huang, Y.-F. Lin, K.-L. Cheng, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "Test scheduling of BISTed memory cores for SOC", in Proc. 11th IEEE Asian Test Symp. (ATS), Guam, Nov. 2002, pp. 356~361.
  120. S.-K. Chiu, J.-C. Yeh, C.-T. Huang, and C.-W. Wu, "Diagonal test and diagnostic schemes for flash memories", in Proc. IEEE Int. Test Conf. (ITC), Baltmore, Oct. 2002, pp. 37~46.
  121. Y.-T. Lin, C.-P. Su, C.-T. Huang, C.-W. Wu, S.-Y. Huang, and T.-Y. Chang, "Low-power embedded memory architecture design for SOC", in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 306~309.
  122. Y.-C. Tsai, S.-Y. Huang, C.-P. Su, C.-T. Huang, and C.-W. Wu, "Fine-grain mixed-level power estimation based on disparity path analysis", in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 199~202.
  123. M.-C. Lee, J.-R. Huang, C.-P. Su, T.-Y. Chang, C.-T. Huang, and C.-W. Wu, "A true random generator design", in Proc. 13th VLSI Design/CAD Symp., Taitung, Aug. 2002, pp. 137~140.
  124. T.-F. Lin, C.-P. Su, C.-T. Huang, and C.-W. Wu, "A high-throughput low-cost AES cipher chip", in Proc. 3rd IEEE Asia-Pacific Conf. on ASIC, Taipei, Aug. 2002, pp. 85~88.
  125. R.-F. Huang, J.-F. Li, J.-C. Yeh, and C.-W. Wu, "A simulator for evaluating redundancy analysis algorithms of repairable embedded memories", in Proc. IEEE Int. Workshop on Memory Technology, Design and Testing (MTDT), Isle of Bendor, France, July 2002, pp. 68~73.
  126. C.-W. Wang, J.-R. Huang, K.-L. Cheng, H.-S. Hsu, C.-T. Huang, C.-W. Wu, and Y.-L. Lin, "A test access control and test integration system for system-on-chip", in 6th IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), Monterey, California, May 2002, pp. P2.1~P2.8.
  127. K.-L. Cheng, J.-C. Yeh, C.-W. Wang, C.-T. Huang, and C.-W. Wu, "RAMSES-FT: A fault simulator for flash memory testing and diagnostics", in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 281~286.
  128. J.-F. Li, R.-S. Tzeng, and C.-W. Wu, "Testing and diagnosing embedded content addressable memories", in Proc. IEEE VLSI Test Symp. (VTS), Monterey, California, Apr. 2002, pp. 389~394.
  129. C.-P. Su and C.-W. Wu, "Graph-based power-constrained test scheduling for SOC", in Proc. IEEE Int. Workshop on Design and Diagnostics of Electronic Circuits and Systems (DDECS), Brno, Czech Republic, Apr. 2002, pp. 61~68 (Best Paper Award).
  130. J.-F. Li, H.-J. Huang, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "A hierarchical test scheme for system-on-chip designs", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Paris, Mar. 2002, pp. 486~490.
  131. C.-W. Wang, R.-S. Tzeng, C.-F. Wu, C.-T. Huang, C.-W. Wu, S.-Y. Huang, S.-H. Lin, and H.-P. Wang, "A built-in self-test and self-diagnosis scheme for heterogeneous SRAM clusters", in Proc. 10th IEEE Asian Test Symp. (ATS), Kyoto, Nov. 2001, pp. 103~108.
  132. J.-F Li, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "March-based RAM diagnosis algorithms for stuck-at and coupling faults", in Proc. IEEE Int. Test Conf. (ITC), Baltmore, Oct. 2001, pp. 758~767.
  133. Y.-F Chou, D.-M. Kwai, and C.-W. Wu, "Optimizing sensitivity of a latched sense amplifier for CMOS SRAM using a simulation-based method", in Proc. 9th Int. Symp. on Integrated Circuits, Devices & Systems (ISIC), Singapore, Sept. 2001.
  134. S.-K. Lu, T.-Y. Lee, and C.-W. Wu, "A profit evaluation system (PES) for logic cores at early design stage", in Proc. 8th IEEE Int. Conf. on Electronics, Circuits and Systems, Malta, Sept. 2001, pp. 1491~1494.
  135. S.-K. Lu, Y.-M. Chen, J.-L. Chen, and C.-W. Wu, "Logic diagnosis based on hardware emulator", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.
  136. H.-C. Kao, M.-F. Tsai, S.-Y. Huang, C.-W. Wu, W.-F. Chang, and S.-K. Lu, "Efficient double fault diagnosis for CMOS logic circuits", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.
  137. J.-B. Chen, J.-F. Li, H.-J. Huang, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "A test controller for system-on-chip designs with test wrappers", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.
  138. H.-J. Huang, J.-F. Li, J.-B. Chen, C.-P. Su, C.-W. Wu, C. Cheng, S.-I Chen, C.-Y. Hwang, and H.-P. Lin, "Test wrapper design automation for system-on-chip", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.
  139. Y.-C. Lin, C.-P. Su, C.-W. Wang, and C.-W. Wu, "A word-based RSA public-key crypto-processor core", in Proc. 12th VLSI Design/CAD Symp., Hsinchu, Aug. 2001.
  140. C.-F. Wu, C.-T. Huang, K.-L. Cheng, C.-W. Wang, and C.-W. Wu, "Simulation-based test algorithm generation and port scheduling for multi-port memories", in Proc. IEEE/ACM Design Automation Conf. (DAC), Las Vegas, June 2001, pp. 301~306.
  141. K.-L. Cheng, M.-F. Tsai, and C.-W. Wu, "Efficient neighborhood pattern-sensitive fault test algorithms for semiconductor memories", in Proc. IEEE VLSI Test Symp. (VTS), Marina Del Rey, California, Apr. 2001, pp. 225~237.
  142. J.-F. Li and C.-W. Wu, "Memory fault diagnosis by syndrome compression", in Proc. Int. Conf. Design, Automation, and Test in Europe (DATE), Munich, Mar. 2001, pp. 97~101.
  143. C.-H. Wu, J.-H. Hong, and C.-W. Wu, "RSA cryptosystem design based on the Chinese Remainder Theorem", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 391~395.
  144. C.-H. Tsai and C.-W. Wu, "Processor-programmable memory BIST for bus-connected embedded memories", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2001, pp. 325~330.
  145. L. Li, X. Yu, C.-W. Wu, and Y. Min, "A waveform simulator based on Boolean process", in Proc. Ninth IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 145~150.
  146. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "A testable/fault-tolerant FFT processor design", in Proc. 9th IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 429~433.
  147. C.-W. Wang, C.-F. Wu, J.-F. Li, C.-W. Wu, T. Teng, K. Chiu, and H.-P. Lin, "A built-in self-test and self-diagnosis scheme for embedded SRAM", in Proc. 9th IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 45~50.
  148. J.-R. Huang, C.K. Ong, K.T. Cheng, and C.-W. Wu, "An FPGA-based reconfigurable functional tester for memory chips", in Proc. 9th IEEE Asian Test Symp. (ATS), Taipei, Dec. 2000, pp. 51~57.
  149. C.-F. Wu, C.-T. Huang, C.-W. Wang, K.-L. Cheng, and C.-W. Wu, "Error catch and analysis for semiconductor memories using March tests", in Proc. IEEE/ACM Int. Conf. on Computer-Aided Design (ICCAD), San Jose, Nov. 2000, pp. 468~471.
  150. C. Cheng, C.-T. Huang, J.-R. Huang, C.-W. Wu, C.-J. Wey, and M.-C. Tsai, "BRAINS: A BIST complier for embedded memories", in Proc. IEEE Int. Symp. on Defect and Fault Tolerance in VLSI Systems (DFT), Yamanashi, Oct. 2000, pp. 299~307.
  151. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "BIST and diagnosis of fully logic blocks in FPGAs", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 413~416.
  152. K.-L. Cheng and C.-W. Wu, "Neighborhood pattern-sensitive fault testing for semiconductor memories", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 401~404.
  153. C.-H. Wu, J.-H. Hong, and C.-W. Wu, "An RSA cryptosystem based on the Chinese Remainder Theorem", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 167~170.
  154. J.-H. Hong, P.-Y. Tsai, and C.-W. Wu, "Interleaving schemes for a systolic RSA public-key cryptosystem based on an improved Montgomery's algorithm", in Proc. 11th VLSI Design/CAD Symp., Pingtung, Aug. 2000, pp. 163~166.
  155. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "Built-in self-test and fault diagnosis for lookup table FPGAs", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Geneva, May 2000, pp. I.80~I.83.
  156. C.-T. Huang, J.-R. Huang, and C.-W. Wu, "A programmable built-in self-test core for embedded memories", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2000, pp. 11~12, (Design contest).
  157. J.-H. Hong and C.-W. Wu, "Radix-4 modular multiplication and exponentiation algorithms for the RSA public-key cryptosystem", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Yokohama, Jan. 2000, pp. 565~570.
  158. S.-K. Lu and C.-W. Wu, "Defect level prediction using multi-model fault coverage", in Proc. 8th IEEE Asian Test Symp. (ATS), Shanghai, Nov. 1999, pp. 301~306.
  159. S.-K. Lu, T.-Y. Lee, and C.-W. Wu, "Defect level prediction using multi-model fault coverage", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 195~198.
  160. S.-K. Lu, J.-S. Shih, and C.-W. Wu, "Testing configurable LUT-based FPGA's", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 171~174.
  161. J.-M. Lu and C.-W. Wu, "Economic analysis of built-in self-test for logic and memory cores", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 203~206.
  162. J.-H. Hong and C.-W. Wu, "A radix-4 cellular array modular multiplier based on Montgomery's algorithm and Booth's algorithm", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 165~168.
  163. S.-H. Shieh and C.-W. Wu, "On r's-complement addition and conversion from asymmetric high-radix signed-digit numbers to binary numbers", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 161~164.
  164. J.-F. Li and C.-W. Wu, "Design for C-diagnosable FFT networks", in Proc. 10th VLSI Design/CAD Symp., Nantou, Aug. 1999, pp. 191~194.
  165. C.-F. Wu and C.-W. Wu, "Fault detection and location of dynamic reconfigurable FPGAs", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, June 1999, pp. 215~218.
  166. S.-K. Lu and C.-W. Wu, "A novel approach to testing LUT-based FPGA's", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Orlando, May 1999, pp. I173~I177.
  167. K.-J. Lin and C.-W. Wu, "PMBC: a programmable BIST compiler for memory cores", in 3rd IEEE Int. Workshop on Testing Embedded Core-Based System-Chips (TECS), Dana Point, Apr. 1999, pp. P2.1~P2.6.
  168. C.-F. Wu and C.-W. Wu, "Testing interconnects of dynamic reconfigurable FPGAs", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Hong Kong, Jan. 1999, pp. 279~282.
  169. C.-W. Wu, "Testing embedded memories: Is BIST the ultimate solution?", in Proc. 7th IEEE Asian Test Symp. (ATS), Singapore, Dec. 1998, pp. 516~517.
  170. C.-W. Wu and C.-Y. Su, "A probabilistic model for path delay faults", in Proc. 7th IEEE Asian Test Symp. (ATS), Singapore, Dec. 1998, pp. 70~75.
  171. Y.-C. Chuang and C.-W. Wu, "On-line error detection schemes for a systolic finite-field inverter", in Proc. 7th IEEE Asian Test Symp. (ATS), Singapore, Dec. 1998, pp. 301~305.
  172. C.-F. Wu and C.-W. Wu, "Testing function units of dynamic reconfigurable FPGAs", in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 189~192.
  173. C.-P. Su, C.-T. Huang, and C.-W. Wu, "DFT methodologies for a communications processor core", in Proc. 9th VLSI Design/CAD Symp., Nantou, Aug. 1998, pp. 161~164.
  174. C.-W. Wu, "On energy Efficiency of VLSI testing", in Proc. 6th IEEE Asian Test Symp. (ATS), Akita, Nov. 1997, pp. 132~137.
  175. S.-K. Lu and C.-W. Wu, "VLSI design of the RSA public-key cryptosystem", in Proc. 7th Int. Symp. on IC Technology, Systems & Applications (ISIC), Singapore, Sept. 1997, pp. 68~71.
  176. Y.-R. Shieh and C.-W. Wu, "Logic testing of switch-level faults for CMOS unate networks", in Proc. 7th Int. Symp. on IC Technology, Systems & Applications (ISIC), Singapore, Sept. 1997, pp. 212~215.
  177. H.-C. Hong and C.-W. Wu, "Optimal integrator gain design of extended MASH high-order S-∆ modulator", in Proc. 8th VLSI Design/CAD Symp., Nantou, Aug. 1997, pp. 333~336.
  178. Y.-C. Chuang and C.-W. Wu, "Concurrent error detection for a systolic Galois-field inverter", in Proc. 8th VLSI Design/CAD Symp., Nantou, Aug. 1997, pp. 77~80.
  179. S.-A. Hwang and C.-W. Wu, "C-testable systolic array design for LZ data compression", in Proc. 8th VLSI Design/CAD Symp., Nantou, Aug. 1997, pp. 81~84
  180. C.-L. Lee, J.-Y. Jou, C.-S. Lin, J.-E. Chen, C.-W. Wu, K.-J. Lee, and C.-C. Su, "A joint project to develop a VLSI testing and design for testability course for universities in Taiwan", in Proc. Int. Conf. on Engineering Education (ICEE), Vol. II, Chicago, Aug. 1997, pp. 43~53.
  181. S.-A. Hwang and C.-W. Wu, "Low-power testing for C-testable iterative logic arrays", in Proc. IEEE Int. Symp. on VLSI Technology, Systems, and Applications (VLSI-TSA), Taipei, June 1997, pp. 355~358
  182. C.-T. Huang and C.-W. Wu, "High-speed C-testable systolic array design for Galois-field inversion", in Proc. European Design and Test Conf. (ED&TC), Paris, Mar. 1997, pp. 342~346.
  183. H.-C. Hong, B.-H. Lin, and C.-W. Wu, "Analysis and design of multiple-bit high-order S-∆ modulator", in Proc. IEEE Asia and South Pacific Design Automation Conf. (ASP-DAC), Chiba, Jan. 1997, pp. 419~424.
  184. S.-H. Shieh, B.-H. Lin, and C.-W.Wu, "Carry-propagation-free adder based on an asymmetric high-radix signed-digit number system", in Proc. Int. Computer Symp. (ICS), Kaohsiung, Dec. 1996, pp. 199~204.
  185. B.-H. Lin, S.-H. Shieh, and C.-W. Wu, "A MISR computation algorithm for fast signature simulation", in Proc. Fifth IEEE Asian Test Symp. (ATS), Hsinchu, Nov. 1996, pp. 213~218.
  186. J.-H. Hong, C.-H. Tsai, and C.-W. Wu, "Hierarchical testing using the IEEE Std 1149.5 Module Test and Maintenance slave interface module", in Proc. 5th IEEE Asian Test Symp. (ATS), Hsinchu, Nov. 1996, pp. 50~55.
  187. H.-C. Hong, S.-H. Shieh, and C.-W. Wu, "Optimization of the spanning tree carry lookahead adder", in Proc. 7th VLSI Design/CAD Symp., Taoyuan, Aug. 1996, pp. 253~256
  188. K.-J. Lin and C.-W. Wu, A low-power CAM design in LZ data compressors", in Proc. 7th VLSI Design/CAD Symp., Taoyuan, Aug. 1996, pp. 225~228.
  189. W.-F. Chang and C.-W. Wu, "A TSC Berger code checker for (2r-1)-bit information", in Proc. 2nd IEEE Int. On-Line Testing Workshop, Biarritz, July 1996, pp. 158~161.
  190. Y.-R. Shieh and C.-W. Wu, "DFT structures for IEEE P1149.4-compatible integrated circuits", in Proc. 2nd IEEE Int. Mixed Signal Testing Workshop, Quebec city, May 1996, pp. 210~215.
  191. P.-S. Chen, S.-A. Hwang, and C.-W. Wu, "A systolic RSA public key cryptosystem", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Atlanta, May 1996, vol. 4, pp. 408~411.
  192. S.-K. Lu, C.-W. Wu, and S.-Y. Kuo, "On fault-tolerant FFT buttery network design", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Atlanta, May 1996, pp. 69~72.
  193. Y.-R. Shieh and C.-W. Wu, "DC control and observation structures for analog circuits", in Proc. 4th IEEE Asian Test Symp. (ATS), Bangalore, Nov. 1995, pp. 120-126, (Reprinted in the 10th Anniversary Compendium of Papers from ATS, pp. 112-118, IEEE, 2001).
  194. C.-Y. Su and C.-W. Wu, "A practical VLSI architecture for RSA public-key cryptosystem", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 273~276.
  195. W.-F. Chang and C.-W. Wu, "Design of TSC Berger code checkers for (2r-1)-bit information", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 132~135.
  196. S.-A. Hwang and C.-W. Wu, "Area-efficient high-speed systolic arrays for Lempel-Ziv data compression", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 212~215.
  197. C.-T. Huang and C.-W. Wu, "High-speed C-testable bit-level systolic arrays for GF(2m) inversion", in Proc. 6th VLSI Design/CAD Symp., Chiayi, Aug. 1995, pp. 136~139.
  198. Y.-L. Li, Y.-C. Lai, and C.-W. Wu, "A cellular-automata chip for fast logic and fault simulation", in Proc. Workshop on CPU Research and Development, Hsinchu, May 1995, pp. 125~130.
  199. S.-K. Lu, S.-Y. Kuo, and C.-W. Wu, "Design and evaluation of fault-tolerant interleaved memory systems", in Proc. 3rd IEEE Asian Test Symp. (ATS), Nara, Nov. 1994, pp. 354~359.
  200. F.-D. Guo, J.-H. Hong, and C.-W. Wu, "Automatic generation of Boundary Scan and BIST circuitry", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 251~256
  201. C.-H. Tsai, J.-H. Hong, and C.-W. Wu, "Built-in self-test techniques using Boundary Scan Standard circuitry", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 257~262
  202. K.-J. Lin and C.-W. Wu, "An area-efficient realization of Exclusive-OR sum-of products expressions", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 143~148.
  203. W.-F. Chang and C.-W. Wu, "Is there a combinational TSC checker for 1/3 code?", in Proc. 5th VLSI Design/CAD Symp., Tainan, Aug. 1994, pp. 199~204.
  204. C.-W. Wu and Y.-F. Chou, "General modular multiplication by block multiplication and table lookup", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), London, May 1994, pp. 295~298.
  205. S.-M. Kao, T. Ning, C.-W. Wu, and H. Peng, "Extraction of the focused objects in an image by filtering out the defocused background", in Proc. IEEE Int. Symp. on Speech, Image Processing, and Neural Networks, Hong Kong, Apr. 1994.
  206. Y.-L. Li and C.-W. Wu, "Logic and fault simulation by massive parallelism", in Proc. NCHC High-Speed Computing Application Workshop, Hsinchu, Apr. 1994, pp. 195~198.
  207. Y.-L. Li and C.-W. Wu, "Logic and fault simulation by cellular automata", in Proc. European Design and Test Conf. (ED&TC), Paris, Feb. 1994, pp. 552~556.
  208. W.-F. Chang and C.-W. Wu, "Design of efficient totally self-checking checkers for m-out-of-n code", in Proc. 2nd IEEE Asian Test Symp. (ATS), Beijing, Nov. 1993, pp. 281~286.
  209. W.-F. Chang and C.-W. Wu, "Totally self-checking checkers for m-out-of-n code with lower hardware complexity", in Proc. 4th VLSI Design/CAD Workshop, Nantou, Aug. 1993, pp. 226~230.
  210. C.-W. Wu and H.-S. Chen, "Cost-effective signature analysis by modular counters", in Proc. 4th VLSI Design/CAD Workshop, Nantou, Aug. 1993, pp. 216~220.
  211. C.-W. Wu and H.-S. Chen, "Modular-addition signature analysis for built-in self-test", in Proc. European Test Conference (ETC), Rotterdam, Apr. 1993, pp. 457~465.
  212. Y.-R. Shieh and C.-W. Wu, "Concurrent error detection of CMOS digital and analog faults", in Proc. European Test Conference (ETC), Rotterdam, Apr. 1993, pp. 74~81.
  213. Y.-F. Chou and C.-W. Wu, "Realization of a practical cellular divider", in Proc. Int. Computer Symp. (ICS), Taichung, Dec. 1992, pp. 1078~1084.
  214. Y.-R. Shieh and C.-W. Wu, "A totally self-checking checker for CMOS stuck-on faults", in Proc. Int. Computer Symp. (ICS), Taichung, Dec. 1992, pp. 1093~1099.
  215. C.-W. Wu, C.-T. Chang, and T.-Y. Chang, "On testable design of FFT buttery networks", in 1992 Int. Conf. on Parallel and Distributed Systems (ICPADS), Hsinchu, Dec. 1992, pp. 190{195.
  216. S.-K. Lu, C.-W. Wu, and S.-Y. Kuo, "Design of easily testable VLSI arrays for discrete Cosine transform", in Proc. IEEE 26th Ann. Asilomar Conf. on Signals, Systems, and Computers, Pacific Grove, Oct. 1992.
  217. C.-W. Wu and J.-C. Wang, "Testable design of bit-level systolic block FIR filters", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), San Diego, May 1992, pp. 1129~1132.
  218. S.-K. Lu, C.-W. Wu, and S.-Y. Kuo, "Testable design of systolic arrays for discrete Cosine transform", in Proc. 1992 VLSI/CAD Workshop, Nantou, Mar. 1992, pp. 228~237.
  219. C.-W. Wu and S.-K. Lu, "Designing self-testable cellular arrays", in Proc. IEEE Int. Conf. on Computer Design (ICCD), Cambridge, Massachusetts, Oct. 1991, pp. 110~113.
  220. C.-W. Wu and S.-K. Lu, "Architecture-specific computer-aided testing", in Proc. Sino-German CAD/VLSI Workshop, Tainan, Sept. 1991, pp. 34~43.
  221. T.-Y. Chang, C.-W. Wu, C.-C. Wang, and J.-B. Shu, "On the design of a fault-tolerant systolic array multiplier using time redundancy", in Proc. Int. Symp. on IC Design and Manufacturing (ISIC), Singapore, Sept. 1991, pp. 497~502.
  222. C.-Y. Lin, Y.-R. Shieh, and C.-W. Wu, "A CMOS 1-out-of-3 totally self-checking checker", in Proc. Int. Symp. on IC Design and Manufacturing (ISIC), Singapore, Sept. 1991, pp. 129~134.
  223. K.-J. Lin and C.-W. Wu, “On easily testable array multipliers”, in Proc. Int. Computer Symp. (ICS), Hsinchu, Dec. 1990, pp. 571~576.
  224. C.-W. Wu, S.-K. Lu, and J.-C. Wang, "Built-in self-test of iterative logic arrays", in Proc. Int. Electron Devices and Material Symp. (EDMS), Hsinchu, Nov. 1990, pp. 485~488.
  225. C.-W. Wu, "Block pipeline 2-D IIR filter structures via iteration and retiming", in Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), New Orleans, May 1990, pp. 731~734.
  226. C.-W. Wu, "Test generation for combinational iterative logic arrays", in Proc. 3rd Int. Symp. on IC Design and Manufacturing (ISIC), Singapore, Sept. 1989, pp. 223~230.
  227. C.-W. Wu and P. R. Cappello, "Computer-aided design of VLSI second-order sections", in Proc. IEEE Int. Conf. on Acoustics, Speech, and Signal Processing (ICASSP), Dallas, Apr. 1987, pp. 1907~1910.
  228. C.-W. Wu and P. R. Cappello, "Application specific CAD of high-throughput IIR filters", in Proc. 32nd IEEE COMPCON, San Francisco, Feb. 1987, pp. 302~305.
專利
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  1. P.-W. Luo, H.-C. Shih, C.- K. Chen, D.-M. Kwai, and C.-W. Wu, "Memory controlling method and memory system", U.S. Patent No. 9905277, Feb. 2018.
  2. P.-W. Luo, H.-C. Shih, C.- K. Chen, D.-M. Kwai, and C.-W. Wu, "Memory controlling method and memory system", R.O.C. Patent No I564893, Jan. 2017 (in Chinese).
  3. S.-Y. Wu and C.-W. Wu, "Data error-detection system and method thereof", R.O.C. Patent No I500272, Sep. 2015 (in Chinese).
  4. C.-W. Wu and H.-C. Shih, "Double through silicon via structure", R.O.C. Patent No I484615, May 2015 (in Chinese).
  5. C.-W. Wu, D.-M. Kwai, C.-C. Li, and K.-Y. Chou, "Image capture device", R.O.C. Patent No I462265, Nov. 2014 (in Chinese).
  6. C.-W. Wu, T.-H. Chen, Y.-Y. Hsiao, and Y.-T. Hsing, "Non-volatile memory management method", R.O.C. Patent No I456578, Oct. 2014 (in Chinese).
  7. C.-W. Wu, P.-Y. Chen, D.-M. Kwai, and Y.-F. Chou, "Method for testing through-silicon-via and the circuit thereof", U.S. Patent No. 8937486, Jan. 2015.
  8. C.-W. Wu, P.-Y. Chen, D.-M. Kwai, and Y.-F. Chou, "Method for testing through-silicon-via and the circuit thereof", R.O.C. Patent No I443353, July 2014 (in Chinese).
  9. H.-C. Shih and C.-W. Wu, "Double through silicon via structure", U.S. Patent No. 8742839, June 2014.
  10. C.-W. Wu, C.-Y. Lo, and Y.-T. Hsing, "Test access control apparatus and method", R.O.C. Patent No I431629, Mar. 2014 (in Chinese).
  11. C.-W. Wu, P.-Y. Chen, D.-M. Kwai, and Y.-F. Chou, "Method for Testing Through-Silicon-Via and the Circuit Thereof", R.O.C. Patent No I411795, Oct. 2013 (in Chinese).
  12. C.-W. Wu, P.-Y. Chen, D.-M. Kwai, and Y.-F. Chou, "Method for Testing Through-Silicon-Via and the Circuit Thereof", U.S. Patent No. 8531199B2, Sept. 2013.
  13. C.-H. Wang, C.-L. Chuang, and C.-W. Wu, "Multiplication Circuit and De/Encryption Circuit Utilizing the Same ", U.S. Patent No. 8443032B2, May 2013.
  14. C.-W. Wu, C.-T. Huang, and Y.-T. Hsing, "Probing System for Integrated Circuit Device", R.O.C. Patent No I392888, Apr. 2013 (in Chinese).
  15. C.-W. Wu, C.-T. Huang, and Y.-T. Hsing, "Probing System for Integrated Circuit Device", R.O.C. Patent No I376516, Nov. 2012 (in Chinese).
  16. C.-W. Wu, T.-H. Chen, Y.-Y. Hsiao, and Y.-T. Hsing, "Non-Volatile Memory Management Method", U.S. Patent No. 8307261B2, Nov. 2012.
  17. M. Lee and C.-W. Wu, "Method for Repairing Memory and System Thereof", R.O.C. Patent No I375959, Nov. 2012 (in Chinese).
  18. C.-H. Wang, C.-L. Chuang, and C.-W. Wu, "Multiplication circuit and de/encryption circuit utilizing the same", R.O.C. Patent No I372353, Sept. 2012 (in Chinese).
  19. M. Lee and C.-W. Wu, "Method for Repairing Memory and System Thereof", U.S. Patent No. 8095832B2, Jan. 2012.
  20. C.-W. Wu, C.-T. Huang, and Y.-T. Hsing, "Probing System for Integrated Circuit Device", U.S. Patent No. 7904768B2, Mar. 2011.
  21. C.-W. Wu, C.-T. Huang, and Y.-T. Hsing, "Probing System for Integrated Circuit Device", U.S. Patent No. 7675309, Mar. 2010.
  22. C.-W. Wu, R.-F. Huang, C.-L. Su, W.-C. Wu, and K.-L. Luo, "Method and Apparatus of Build-In Self-Diagnosis and Repair in a Memory with Syndrome Identification", U.S. Patent No. 7644323, Jan. 2010.
  23. C.-W. Wu, C.-L. Su, and Y.-T. Yeh, “Semiconductor Memory and Method of Correcting Error for the Same”, R.O.C. Patent No. I289851, Nov. 2007 (in Chinese).
  24. C.-W. Wu, R.-F. Huang, C.-L. Su, W.-C. Wu, Y.-J. Chang, K.-L. Luo, and S.-T. Lin, "Method and Apparatus of Build-In Self-Diagnosis and Repair in a Memory with Syndrome Identification", U.S. Patent No. 7228468, June 2007.
  25. C.-W. Wu, J.-C. Yeh, and H.-H. Ou, "Method and apparatus for multiple polynomial-based random number generation", R.O.C. Patent No. I269222, Dec. 2006 (in Chinese).
  26. S.-K. Chiu, J.-C. Yeh, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "Diagonal testing method for flash memories", U.S. Patent No. 7065689, June 2006.
  27. C.-W. Wu, C.-T. Huang, and Y.-T. Hsing, "Probing system for integrated circuit devices", R.O.C. Patent No. I264551, Oct. 2006.
  28. C.-W. Wu, C.-T. Huang, C.-W. Wang, and K.-L. Cheng, "Multi-port memory testing method utilizing a sequence folding scheme for testing time reduction", U.S. Patent No. 7117409, Oct. 2006.
  29. C.-W. Wu, C.-T. Huang, C.-W. Wang, and K.-L. Cheng, "Method of multi-port memory test and computer readable recording medium", R.O.C. Patent No. I252974, Apr. 2006 (in Chinese).
  30. C.-W. Wu, R.-F. Huang, C.-L. Su, W.-C. Wu, Y.-J. Chang, K.-L. Lo, and S.-T. Lin, "Method and apparatus of built-in self-diagnosis and repair in a memory with syndrome identification", R.O.C. Patent No. I252397, Apr. 2006 (in Chinese).
  31. C. Cheng, C.-T. Huang, J.-R. Huang, and C.-W. Wu, "Test pattern generator for SRAM and DRAM", U.S. Patent No. 6934900, Aug. 2005.
  32. C.-W. Wu, J.-R. Huang, C.-F. Wu, and C.-T. Huang, "Built-in self-test circuit for embedded memory", R.O.C. Patent No. 200758, Apr. 2004 (in Chinese).
  33. S.-K. Chiu, J.-C. Yeh, K.-L. Cheng, C.-T. Huang, and C.-W. Wu, "Diagonal test schemes for flash memories", R.O.C. Patent No. 192282, Dec. 2003 (in Chinese).
  34. C.-F. Wu, C.-W. Wang, J.-F. Li, C.-W. Wu, C.-C. Teng, and C.-K. Chiu, "Built-in programmable self-diagnostic method and circuit for SRAM", R.O.C. Patent No. 169346, Dec. 2002 (in Chinese).
  35. C.-F. Wu, C.-W. Wang, J.-F. Li, C.-W. Wu, C.-C. Teng, and C.-K. Chiu, "Built-in programmable self-diagnostic circuit for SRAM unit", U.S. Patent No. 6529430, Mar. 2003 (Claiming diagnostic circuit).
  36. J.-R. Huang, C.-T. Huang, C.-F. Wu, and C.-W. Wu, "Programmable built-in self-test for embedded DRAM", U.S. Patent No. 6415403, July 2002.
  37. C.-H. Tsai, F.-D. Guo, J.-H. Hong, and C.-W. Wu, "IEEE Std. 1149.1 boundary scan circuit capable of built-in self-testing", U.S. Patent No. 5570375, Oct. 1996.
其他
more
less
  1. K.-W. Hou and C.-W. Wu, "The Fate of IOT Relies on AI and Semiconductor",
  2.  C.-W. Wu, “Can IOT make semiconductor great again?”, in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2017.
  3. C.-W. Wu, H. Fujiwara, X. Li, K.-J. Lee, and S. Kajihara "25th Anniversary Panel Session: Past, Present, and Future of ATS," in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (Panel Discussion Session).
  4. C.-W. Wu, "Symbiotic-System Approach for IOT Devices," in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (McCluskey Keynote Speech).
  5. C.-W. Wu, "Is IOT Coming to the Rescue of Semiconductor?" in Proc. 21st IEEE European Test Symp. (ETS), Amsterdam, May 2016 (Keynote Speech).
  6. B.-Y. Lin and C.-W. Wu, “Redundancy Architectures and Analysis Methodologies for 3D Memories Yield Improvement,” in Proc. IEEE Int. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Seattle, Washington, Oct. 2014 (Special Session: Ongoing PhD Research in 3D-Test).
  7. C.-W. Wu, "Holistic Approach to Low-Power System Design", in Proc. IEEE Int. Symp. on Low Power Electronics and Design (ISLPED), Beijing, Sept. 4-6, 2013 (Keynote Speech).
  8. J.-F. Li, C.-W. Wu, M. Aoyagi, M.-F. Chang, and D.-M. Kwai, “3D-IC Design and Test”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013 (Special Session 4C: Hot Topic).
  9. C.-W. Wu and M.-S. Lee, "Memory yield and reliability enhancement methodology for nano-scale SOC",
  10. C.-W. Wu, "An OEM family",
  11. C.-W. Wu, "What has SOC to do with you?",
  12. C.-W. Wu, "The high-tech nomadic",
  13. C.-P. Su, M.-Y. Wang, and C.-W. Wu, "Introduction to crypto-processor",
  14. C.-W. Wang, C.-F. Wu, J.-F. Li, R.-F. Huang, and C.-W. Wu, "SRAM built-in self-test and built-in self-diagnosis",
  15. C.-W. Wu, C.-T. Huang, and C.-Y. Wu, "2001 International Workshop on IC-SOC",
  16. C.-W. Wu, "Foreword for the Special Issue on Design and Test of System-on-Chip",
  17. C.-W. Wu and C.-T. Huang, "VLSI Test Technology Forum",
  18. C.-W. Wu, C.-H. Wu, and Y.-L. Lin, "Communications IP: Development of a low-power communications processor core",
  19. C.-T. Huang and C.-W. Wu, "Overview of memory testing technology",
  20. C.-W. Wu, "Pioneers of SOC design: NTHU IC Design Technology Center",
  21. C.-W. Wu, "Should we worry about pennies for power?",
  22. C.-W. Wu, "Design of testable iterative logic arrays for DCT",
其他
more
less
  1. K.-W. Hou and C.-W. Wu, "The Fate of IOT Relies on AI and Semiconductor",
  2.  C.-W. Wu, “Can IOT make semiconductor great again?”, in Proc. Int. Symp. on VLSI Design, Automation, and Test (VLSI-DAT), Hsinchu, Apr. 2017.
  3. C.-W. Wu, H. Fujiwara, X. Li, K.-J. Lee, and S. Kajihara "25th Anniversary Panel Session: Past, Present, and Future of ATS," in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (Panel Discussion Session).
  4. C.-W. Wu, "Symbiotic-System Approach for IOT Devices," in Proc. 25th IEEE Asian Test Symp. (ATS), Hiroshima, Nov. 2016 (McCluskey Keynote Speech).
  5. C.-W. Wu, "Is IOT Coming to the Rescue of Semiconductor?" in Proc. 21st IEEE European Test Symp. (ETS), Amsterdam, May 2016 (Keynote Speech).
  6. B.-Y. Lin and C.-W. Wu, “Redundancy Architectures and Analysis Methodologies for 3D Memories Yield Improvement,” in Proc. IEEE Int. Workshop on Testing Three-Dimensional Stacked Integrated Circuits (3D-TEST), Seattle, Washington, Oct. 2014 (Special Session: Ongoing PhD Research in 3D-Test).
  7. C.-W. Wu, "Holistic Approach to Low-Power System Design", in Proc. IEEE Int. Symp. on Low Power Electronics and Design (ISLPED), Beijing, Sept. 4-6, 2013 (Keynote Speech).
  8. J.-F. Li, C.-W. Wu, M. Aoyagi, M.-F. Chang, and D.-M. Kwai, “3D-IC Design and Test”, in Proc. 31st IEEE VLSI Test Symp. (VTS), Berkeley, CA, Apr. 2013 (Special Session 4C: Hot Topic).
  9. C.-W. Wu and M.-S. Lee, "Memory yield and reliability enhancement methodology for nano-scale SOC",
  10. C.-W. Wu, "An OEM family",
  11. C.-W. Wu, "What has SOC to do with you?",
  12. C.-W. Wu, "The high-tech nomadic",
  13. C.-P. Su, M.-Y. Wang, and C.-W. Wu, "Introduction to crypto-processor",
  14. C.-W. Wang, C.-F. Wu, J.-F. Li, R.-F. Huang, and C.-W. Wu, "SRAM built-in self-test and built-in self-diagnosis",
  15. C.-W. Wu, C.-T. Huang, and C.-Y. Wu, "2001 International Workshop on IC-SOC",
  16. C.-W. Wu, "Foreword for the Special Issue on Design and Test of System-on-Chip",
  17. C.-W. Wu and C.-T. Huang, "VLSI Test Technology Forum",
  18. C.-W. Wu, C.-H. Wu, and Y.-L. Lin, "Communications IP: Development of a low-power communications processor core",
  19. C.-T. Huang and C.-W. Wu, "Overview of memory testing technology",
  20. C.-W. Wu, "Pioneers of SOC design: NTHU IC Design Technology Center",
  21. C.-W. Wu, "Should we worry about pennies for power?",
  22. C.-W. Wu, "Design of testable iterative logic arrays for DCT",
-->
研究計劃
開授課程
指導學生
本學年度 實驗室成員
碩士班
李柏賢
陳彥名
林元祥
林獻昱
程亞淇
周昱佑
杜冠勳
已畢業學生
特殊榮譽
  1. IEEE 2016 Asian Test Symposium (ATS, Hiroshima) Best Paper Award(2017)
  2. IEEE ATS 25th Anniversary “Most Influential Paper Award”(最具影響力論文獎)(2016)
  3. 1. IEEE ATS 25th Anniversary “Most Contribution Author Award”(最多論文貢獻獎)(2016)
  4. 中國電機工程學會『電機工程獎章』(2015)
  5. 科技部傑出技術移轉貢獻獎(2014)
  6. 1. 清華特聘講座教授(2014)
  7. 1. 教育部第17屆國家講座主持人(2013)
  8. 1. 國家產業創新獎卓越創新研究機構獎(2013,代表資通所)
  9. 中華民國科技管理學會 Fellow(2013)
  10. 國立清華大學智財商化績優教師(2012)
  11. NSOC國科會服務貢獻獎-奈米級晶圓之無線測試與特性擷取技術(2011)
  12. 晶片系統國家型科技計畫(NSOC)卓越計畫獎-奈米級晶圓之無線測試與特性擷取技術(2011)
  13. 東元獎(2010)
  14. 1. 國科會傑出研究獎(2009-2012)
  15. 國家發明獎銀牌(2009)
  16. 台南一中校友傑出成就獎(2008)
  17. 國科會NSOC整合型學術研究計畫研究成果展績優獎(2008)
  18. 清華大學傑出產學合作獎(2007)
  19. The 18th VLSI Design/CAD Symposium Best Paper Award(2007)
  20. IEEE VLSI Test Symposium(VTS)Best Innovative Practices Session Award(2007)
  21. 清華大學清華講座教授(2006)
  22. 國科會技術移轉個案獎勵(2006)
  23. 清華大學傑出教學獎(2006)
  24. Golden Core Member, IEEE Computer Society(2006)
  25. Outstanding Contribution Award, IEEE Computer Society(2005)
  26. Continuous Service Award, IEEE Computer Society(2005)
  27. 1. 教育部學術獎(2005)
  28. IEEE Fellow(2004)
  29. 國科會CIC設計特優獎(2004)
  30. NSOC傑出創新成果獎(2004)
  31. 國科會技術移轉個案獎勵(2003)
  32. IEEE 2003 ASP-DAC Best Paper Award(2003)
  33. IEEE 2003 Asia and South Pacific Design Automation Conf. (ASP-DAC) IC Design Contest Best Features Award(2003)
  34. IEEE 2002 Int. Workshop on Design and Diagnostics of Electronic Circuits and Systems(DDECS)Best Paper Award(2002)
  35. 教育部產學合作獎(博士生組,2003)
  36. 教育部產學合作獎(教師組,2001)
  37. 國科會傑出研究獎(2002-2005)
  38. 國科會傑出研究獎(2000-2001)
  39. IEEE Computer Society Certificates of Appreciation(1997, 2001, 2003, 2005, 2006, 2007, 2016)
  40. 中國電機工程學會傑出電機工程教授獎(1997)
  41. 清華大學傑出教學獎(1996)
  42. 教育部公費留考資訊工程學門第一名(1983)
  43. 高考電機技師(1982)