國立成功大學電機工程學系 教師個人頁面
English Version
陳盈如 副教授
地址
奇美系館6樓95607室
Email
TEL
06-2757575 ext.62321
實驗室網站連結
電腦輔助驗證實驗室
(R95614/ext.62400-2817)
學經歷
學歷
2014
台灣大學電子工程博士
2006
中正大學資訊工程碩士
2002
交通大學資訊工程學士
經歷
2016/08-迄今
國立成功大學電機系助理教授
2015/05-2016/07
益華電腦股份有限公司應用工程副理
2014/05-2015/01
聯發科技股份有限公司資深工程師
2002/07-2003/09
工業技術研究院助理工程師
研究領域
  • 正規方法, 包括模型驗證, 定理證明 等
  • 功能安全驗證之方法論建立
  • 資料/晶片之安全驗證
  • 數位電路設計
  • 人工神經網路應用於驗證領域之研究
  • 量子電路設計與驗證
著作
期刊論文( Journal )
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  1. Chen, Y. R., Hsu, C. H., Li, T. F., Lin, C. Y., Weng, S. C. & Tsai, M. Y., “Automatic Model Transformation and Formal Verification for Function Block of IEC 61499,” Software and Systems Modeling, Accepted/In press, 2025.
  2. Wang, Y. T., Lin, T. Y., Sou, S. I., Chen, L. A., Tsai, M. H., Chen, Y. R. & Tu, C. H., “Markov Clustering-Based Content Placement in Roadside-Unit Caching With Deadline Constraint,” IEEE Transactions on Intelligent Transportation Systems, 25(9), pp. 11881-11892, 2024.
  3. Chen, Y. R., Chiu, C. C. & Chen, H., “Robustness Analysis of Neural Network Designs with Sparsity Investigation,” Journal of Information Science and Engineering, 40(3), pp. 595-614, May 2024.
  4. Chen, Y. R., Wang, T. F., Chen, S. H. & Kao, Y. C., “Empirical study on security verification and assessment of neural network accelerator,” Microprocessors and Microsystems, Vol. 99, June 2023, 104845.
  5. Chen, Y. R., Chen, S. H. & Lin, S. W., “SMT Solver With Hardware Acceleration,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 42(6), pp. 2055-2068, June 2023.
  6. Lin, T. Y., Wang, C. Y., Tuan, Y. P., Tsai, M. H. & Chen, Y. R., “A Study on Traffic Asymmetry for Detecting DDoS Attack in P4-based SDN,” Journal of Information Science and Engineering, 38(6), pp. 1265-1283, Nov. 2022.
  7. Y.-R. Chen, J.-J. Yeh, P.-A. Hsiung, and S.-J. Chen, “Accelerating Coverage Estimation through Partial Model Checking,” IEEE Transactions on Computers, Computer 63(7): pp. 1613-1625, 2014.
  8. C.-S. Lin, P.-A. Hsiung, S.-W. Lin, Y.-R. Chen, C.-H. Lu, S.-Y. Tong, W.-T. Su, W. C. Chu, C.-H. Shih, N.-L. Hsueh, C.-H. Chang, and C.-S. Koong, "VERTAF/Multi-Core: A SysML-based Application Framework for Multi-Core Embedded Software Development," Journal of the Chinese Institute of Engineers, Vol. 32, No. 7, pp. 985-991, November 2009 (SCI).
  9. P.-A.Hsiung, S.-W.Lin, Y.-R.Chen, C.-H.Huang, and W. C. Chu, "Modeling and Verification of Real-Time Embedded Systems with Urgency," Journal of Systems and Software (JSS) (SCI), Volume 82, No. 10, pp. 1627-1641, Elsevier Inc., October 2009.
  10. P.-A. Hsiung, Y.-R. Chen and Y.-H. Lin, "Model Checking Safety-Critical Systems using Safecharts," IEEE Transactions on Computers (SCI), Vol. 56, No. 5, pp. 692-705, May 2007.
  11. Y.-R. Chen and P.-A. Hsiung, "Automatic Failure Analysis using Safecharts," International Journal of Software Engineering and Knowledge Engineering (IJSEKE) (SCI), Vol. 17, No. 1, pp. 57-78, World Scientific Publishing, Singapore, February 2007.
會議論文( Conference )
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  1. Ting, C. C., Huang, Y. T., Chen, Y. T., Chen, Y. R. & Lin, E. H., “Spectre Attack Detection with Formal Method on RISC-V Processor at RTL Design Level,” VLSI TSA 2025 - Proceedings of Technical Papers, IEEE, 2025.
  2. Lin, C. C., Yan, J. Q. & Chen, Y. R., “Stabilizer-Based Dynamic Assertion Circuits (SBDACs) for Quantum Circuits,” VLSI TSA 2025 - Proceedings of Technical Papers, IEEE, 2025.
  3. Lin, S. W., Wang, T. F., Chen, Y. R., Hou, Z., Sanán, D. & Teo, Y. S., “A Parallel and Distributed Quantum SAT Solver Based on Entanglement and Teleportation,” TACAS 2024, ETAPS 2024, Proceedings, LNCS 14571, Springer, pp. 363-382, 2024.
  4. Lin, C. N., Lin, S. W. & Chen, Y. R., “Dynamic Assertions for Quantum Circuits Based on Stabilizers,” Quantum Technologies 2022, SPIE Proceedings, Vol. 121330, 2022.
  5. Lin, C. H., Su, Y. P., Chen, Y. R., Chou, Y. T. & Chen, S. J., “Empirical Study of Proposed Meltdown Attack Implementation on BOOM v3,” MWSCAS 2022 - 65th IEEE International Midwest Symposium on Circuits and Systems, Proceedings, 2022.
  6. Chen, H., Su, Y. P., Chen, Y. R., Chiu, C. C. & Chen, S. J., “Robustness Analysis of Neural Network Designs for ReLU Family and Batch Normalization,” IC TAAI 2022 - Proceedings of 2022 International Conference on Technologies and Applications of Artificial Intelligence, IEEE, pp. 1-6, 2022.
  7. Ke, C. S. & Chen, Y. R., “Instruction Verification of Ethereum Virtual Machine by Formal Method,” Indo-Taiwan ICAN 2020 - Proceedings, IEEE, pp. 69-74, Feb. 2020.
  8. Y.-R. Chen, S.-J. Chen, P.-A. Hsiung, I-H. Chou, “Unified Security and Safety Risk Assessment - A Case Study on Nuclear Power Plant,” TSA 2014: 22-28
  9. Y.-R. Chen, Z.-R. Wong, P.-A. Hsiung, S.-J. Chen and M.-H. Tsai, “Backward Probing Deadlock Detection for Networks-on-chip,” International Symposium on Networks-on-Chip (NOCS), April 2013.
  10. H.-L. Chao, Y.-R. Chen, S.-Y. Tong, P.-A. Hsiung, S.-J. Chen, “Congestion-aware scheduling for NoC-based reconfigurable systems,” Design, Automation & Test in Europe Conference & Exhibition (DATE), March 2012.
  11. Y.-R. Chen , W.-T. Su, P.-A. Hsiung, Y.-C. Lan, Y.-H. Hu, and S.-J. Chen, "Formal Modeling and Verification of Network-on-Chip," Proceedings of the International Conference on Green Circuits and Systems, 2010.
  12. Y.-R. Chen, T.-Y. Chen, P.-A. Hsiung, S.-J. Chen and Y.-H. Hu, "Compositional Automata Reduction with Non-critical Path Slicing," The 2009 International Conference on Foundations of Computer Science, pp. 133-138, CSREA Press, July 2009.
  13. P.-A. Hsiung, C.-S. Lin, S.-W. Lin, Y.-R. Chen, C.-H. Lu, S.-Y. Tong, W.-T. Su, C. Shih, C.-S. Koong, N.-L. Hsueh, C.-H. Chang, William C. Chu, "VERTAF/Multi-Core: A SysML- based Application Framework for Multi-Core Embedded Software Development," Proceedings of the International Conference on Algorithms and Architectures for Parallel Processing (ICA3PP), LNCS, Springer Verlag, June 2009.
  14. P.-A. Hsiung, S.-W. Lin, Y.-R. Chen, N.-L. Hsueh, C.-H. Chang, C.-H. Shih, C.-S. Koong, C.-S. Lin, C.-H. Lu, S.-Y. Tong, W.-T. Su, and W. C. Chu, "Model-Driven Development of Multi-Core Embedded Software," Proceedings of the 2nd International Workshop on Multicore Software Engineering (IWMSE), May 2009.
  15. Y.-R. Chen, P.-A. Hsiung, and S.-J. Chen, "Modeling and Automatic Failure Analysis of Safety-Critical Systems using Extended Safecharts," Proceedings of the International Conference on Computer Safety, Reliability and Security (SAFECOMP, Nuremberg, Germany), Lecture Notes in Computer Science (LNCS), Springer Verlag, September 2007.
  16. P.-A. Hsiung , S.-W. Lin, Y.-R. Chen, C.-H. Huang, J.-J. Yeh, H.-Y. Sun, C.-S. Lin, and H.-W. Liao, "Model Checking Timed Systems with Urgencies," Proceedings of the 4th International Symposium on Automated Technology for Verification and Analysis (ATVA, Beijing, China), LNCS Vol. 4218, pp. 67-81, Springer-Verlag, October 2006.
  17. S.-W. Lin, P.-A. Hsiung , C.-H. Huang, and Y.-R. Chen, "Model Checking Prioritized Timed Automata," Proceedings of the 3rd International Symposium on Automated Technology for Verification and Analysis (ATVA, Taipei, Taiwan), LNCS Vol. 3707, pp. 370-384, Springer Verlag, October 2005.
專利
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其他
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  1. Ebook Editor: P.-A. Hsiung , Y.-H. Lin, and Y.-R. Chen, "Safecharts Model Checking for the Verification of Safety-Critical Systems," in Verification, Validation and Testing in Software Engineering , editors Aristides Dasso, Ana Funes, IDEA Group, Inc., USA, ISBN: 1-59140-851-2, 2007.
  2. Invited Reviewer of IEEE Transactions on Computers
  3. Invited Reviewer of International Symposium on Automated Technology for Verification and Analysis
研究計劃
  1. Principal Investigator: Formal Verification (RealTek, Inc.) , 2018/03 -
  2. Principal Investigator: Development of a Scalable Formal Verification, Failure and Causality Analysis Tool Set for Safety-Critical Internet-of-Things Systems (MOST 106 - 2218 - E - 006 - 012), 2017/03 - 2018/02
  3. Project Executor: Research on Information Security and Asset Management in Nuclear Power Plants (Project code: 1002001INER001), 2011/01-2011/12
  4. Project Executor: National Science Council sponsored International Collaboration Research Project (NSC 97-2221-E002-241-MY3),Research on the Development of a Hierarchical Network-on-Chip System Platform Synthesizer, 2008-2011
  5. Project Executor: National Taiwan University and SpringSoft (Synopsys) Inc. , Electronic System Level (ESL) Design Project, 2007-2008
開授課程
113學年度下學期
113學年度上學期
112學年度下學期
112學年度上學期
111學年度下學期
111學年度上學期
110學年度下學期
110學年度上學期
109學年度下學期
109學年度上學期
108學年度下學期
108學年度上學期
107學年度下學期
107學年度上學期
106學年度下學期
106學年度上學期
指導學生
本學年度 實驗室成員
碩士班
蔡旻諺
鄧兆鈞
李翊廷
沈育賢
陸啟倫
李天富
王靖惟
顏吉慶
張珈瑋
許禮均
陳俐蓉
陳語彤
吳念泓
李舜宇
謝承愷
賴郁明
鐘敬堯
顏堃瑋
陳柏聖
洪伯翰
已畢業學生
碩士班
106
呂明霖   劉彥廷
107
連晉瑋   巫世偉   高振庭   高義鈞
108
許嘉豪   鄭天胤   柯春生
110
譚力銘   黃聖龍   楊佳憲   陳航   丁之正   黃煜庭   陳思翰   王琦凱
111
周育霆   翁紹嘉   林健湘   林呈遠
112
王朝宇   林冠名   邱繼頡   韋盛然   顏子傑   王梓帆
特殊榮譽
  1. 威斯康辛大學麥迪遜分校訪問學者(Visiting Scholar), the University of Wisconsin-Madison, Madison Madison, WI, USA, Department of Electrical and Computer Engineering, 2009.
  2. Annual Excellent Thesis Award of Institute of Information & Computing Machinery, 2006.
NCKU EE