Jer-Min Jou, Chien-Ming Sun, Chen-Yen Lin, Yun-Lung Lee, Yuan-Long Jeang, “Design of a Novel Reconfigurable Arithmetic Unit Array Architecture,” to be published in the International Journal of Electrical Engineering, 2007.

Yuan-Long Jeang, Jer-Min Jou, Win-Hsien Huang, “A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2006.

Jer Min Jou, Chien-Ming Sun, Hong-Yi Su, Shih-Hsun Hsu and Ming-Chao Lee “Run-Time Multi-tile Reconfigurable Hardware Platform Design for Multimedia Applications,” The invited journal papers of Avtometriya, Russia, 2005.

Y.-H. Shiau, J.M. Jou, and C.-C. Liu, “Efficient Architectures for the Biothogonal Wavelet Transform by Filter Bank and Lifting Scheme,” IEICE Transactions on Information and Systems, July, 2004.

Y.-H. Shiau and J.M. Jou, "A High-Performance Tree-Block Pipelining Architecture for Separable 2-D Inverse Discrete Wavelet Transform," IEICE Transactions on Information and Systems, vol. E86-D, no. 10, pp. 1966-1975, 2003.

J.M. Jou, S.R. Kuang, and Y.-H. Shiau "Dynamic Pipelined Architecture for Fuzzy Color Correction,"IEEE Trans. On VLSI, pp.924-928, 2003.

R.-D. Chen and J.M. Jou, "STG-level decomposition and resynthesis of speed-independent circuits," IEEE Transactions on Circuits & Systems Part I, pp.1151-1163, Dec., 2002, USA.

J.M. Jou, Y.-H. Shiau, P.-Y. Chen, and S.-R. Kuang, "A Low Cost Gray Prediction Search Chip for Motion Estimation," IEEE Transactions on Circuits & Systems Part I, pp. 928-928, July, 2002, USA.

S.-R. Kuang, J.M. Jou, R.-D. Chen, Y.-H. Shiau, "Dynamic Pipeline Design of an Adaptive Binary Arithmetic Coder," IEEE Transactions on Circuits & Systems Part II, pp.813-825, Sept. 2001, USA.

P.-Y. Chen and J.M. Jou, "An Efficient Block-Matching Algorithm Based on Fuzzy Reasoning," IEEE Trans. on System, Man, and Cybernetics, vol.31, no.2, pp.253-259, 2001, USA.

J.M. Jou, P.-Y. Chen and S.-F. Yang, "An Adaptive Fuzzy Logic Controller: Its VLSI Architecture and Applications," IEEE Trans. on VLSI, vol. 8, no. 1, pp.52-60, Jan. 2000, USA.

J.M. Jou and P.-Y. Chen "Adaptive Arithmetic Coding Using Fuzzy Reasoning and Gray Theory," International Journal for Fuzzy Sets and Systems, vol.114, no.2, pp.239-254, 2000.

J.M. Jou, S.-R. Kuang, and R. D. Chen, “Design of Low-Error Fixed-Width Multipliers for DSP Applications,” IEEE Transactions on Circuits & Systems Part II, vol.46, no.6, pp.836-842, June 1999.

J.M. Jou and P.-Y. Chen "A Fast and Efficient lossless Data Compression Method," IEEE Trans. On Communications, vol.47, no.9, pp.1278-1283, 1999.

J.M. Jou, S.-R. Kuang and R. D. Chen "A New Efficient Fuzzy Algorithm for Color Correction," IEEE Trans. on Circuits & Systems Part I, vol. 46, no. 6, pp.773~775, 1999.

P.-Y. Chen, and J.M. Jou "A Fast-Search Motion Estimation Method and its VLSI Architecture," IEEE Trans. On Circuits and Systems Part II, vol. 46, no. 9, pp.1233-1240, 1999.

J.M. Jou, P.-Y. Chen, and J.-M. Sun "The Gray Prediction Search Algorithm for Block Motion Estimation," IEEE Transactions on Circuits & Systems for Video Technology, vol.9, no.6, pp.843-848, 1999, USA.

S.-R. Kuang, J.M. Jou and Y.-L. Chen "The Design of an Adaptive On-Line Binary Arithmetic Coding Chip," IEEE Trans. on Circuits & Systems Part I, Vol.45, No.7, pp.693-706, 1998.

S.-C. Chen and J.M. Jou, "Diagnostic Fault Simulation for Synchronous Sequential Circuit," IEEE Trans. on CAD, vol.17, no.3, pp.299-308, 1997.

J.M. Jou and S.R. Kuang, "Design of a low-error fixed-width multiplier for DSP applications" Electronic Letters, vlo.33, no.19, pp.1597-1598, 1997.

W.-H. Chang, Jer Min Jou, C.-H. Hsieh, and D.-Y. Lin : A Distributed Run-Time Dynamic Data Manager for Multi-core System Parallel Execution, J.-S. Pan et al. (Eds): Advances in Intelligent Systems & Applications, Vol.2, SIST 21, pp. 741-750, 2012.

S. H., Jer Min Jou, C.-H. Hsieh, and D.-Y. Lin : Design of a Dynamic Parallel Execution Architecture for Multi-Core Systems, J.-S. Pan et al. (Eds): Advances in Intelligent Systems & Applications, Vol.2, SIST 21, pp. 731-740, 2012.

Jer Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang, “New model-driven design and generation of multi-facet arbiters part I: From the design model to the architecture model”, Design Automation Conference (DAC), 2010 47th ACM/IEEE.

Jer Min Jou, Yun-Lung Lee, Sih-Sian Wu, "Efficient design and generation of a multi-facet arbiter",Application Specific Processors (SASP), 2010 IEEE 8th Symposium on

Yun-Lung Lee, Jer Min Jou and Yen-Yu Chen,"A High-Speed and Decentralized Arbiter Design for NoC", The 7th ACS/IEEE International Conference on Computer Systems and Applications 2009

Jer Min Jou, Yun-Lung Lee, Ren-Der Chen, Sih-Sian Wu, Cheng Chou, and Yen-Yu Chen,"Design Space Exploration and Construction of an Arbiter Design Model", National Computer Symposium 2009

Yun-Lung Lee, Jer Min Jou, ” Design of A Reconfigurable Floating-Point Unit”, International Computer Symposium, pp.294 ~ pp.298, ICS 2008

Yun-Lung Lee, Jer Min Jou, Yen-Yu Chen, Sih-Sian Wu, “A Optimal Arbiter Design for NoC”, International Computer Symposium, pp.288 ~ pp.293, ICS 2008

Yun-Lung Lee, Jun-Wei Yang, and Jer Min Jou, "Design of a Distributed JPEG Encoder on a Scalable NoC Platform", VLSI-DAT,2008

Jer Min Jou, Y.-L. Lee, and C.-Y. Lin, “A Novel Reconfigurable Computation Unit for DSP Applications”,The IEEE Computer Society Annual Symposium on VLSI, 2007

Shih-Hsun Hsu, Yu-Xuan Lin and Jer-Min Jou, “Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs”, Asian Solid-State Circuits Conference (A-SSCC) 2006, 13-15, November, 2006.

Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee, Chien-Ming Sun, “An Effieient NoC Pipelined Router Design”, International Conference on Computer & Communication Engineering (ICCCE '06), 9-11, May, 2006.

Shih-Hsun Hsu, Zi-Lun Wang, Jer-Min Jou, Ming-Chao Lee, Chien-Ming Sun, “A Low Power Routing ASIP for NoC”, International Conference on Computer & Communication Engineering (ICCCE '06), 9-11, May, 2006.

Jer Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Ming-Chao Lee, Ye-Xuan Yan, Hong-Yi Su, and Haoi Yang, “A Multi-tile Reconfigurable Platform Design for DSP Applications,” ACIT-SIP 2005, Novosibirsk, Russia, June 20-24, 2005.

Shih-Lun Chen, Jer-Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Haoi Yang, Hong-Yi Su,"Reconfigurable Processor Core Design for Network-on-a-Chip," International Computer Symposium, 2004.

J. M. Jou et. al., "System Design of NoC”, Proceedings of the 2003 MiddleEast Circuits & Systems Conference, 2003.

Kuang-Li Wu, Jer-Min Jou, Yeu-Horng Shiau, and Ren-Der Chen, “Bus Wrapper Design Methodology in SoC, ” Proceedings of 2002 International Computer Symposium, 2002.

Yeu-Horng Shiau, Jer-Min Jou and Tsung-Chih Wang, “Design of Modular Scalable HMM-based Continuous Speech Recognition / Convolutional Decoder IP, ” Proceedings of 2002 International Computer Symposium, 2002.

J. M. Jou, S.-R. Kuang, and K.-M. Wu, "A Hierarchical Interface Design Methodology And Models For SoC IP Integration," IEEE International Symposium On Circuits and Systems, pp.360 –363, 2002.

Jer Min Jou, Yeu Horng Shiau and Bu Ren Zheng, “A novel motion estimation algorithm and its VLSI architecture,” Proceedings of 2002 IEEE Asia-Pacific Conference on ASIC, pp. 241-244, 2002.

J. M. Jou, Y.-H. Shiau, and C.-C. Liu, "Efficient VLSI Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme," IEEE International Symposium On Circuits and Systems, pp. 529-533, 2001.

Y.-H. Shiau and J.M. Jou, “A tree-block Scheduling Architecture for Separable 2-D Inverse Discrete Wavelet Transform”, International Computer Symposium, Workshop on Image Processing and Pattern Recognition, 2000.

J.M. Jou, P.-Y. Chen, Y.-H. Shiau, and J.-M. Sun, “A grey prediction motion estimator for digital image processing”, The 6th IEEE International Conference on Electronics, Circuits and Systems, Proceedings of ICECS '99, Vol. 2, pp. 701-704, 1999.

J.M. Jou, S.-R. Kuang and Y.-H. Shiau “A New Pipelined Architecture for Fuzzy Color Correction,” Proc. of Asia and South Pacific Design Automation Conference, pp.209-212, 1999.

Y.-H. Shiau, P.-Y. Chen, and J. M. Jou, “A gray-based block-matching algorithm and its VLSI architecture”, 1999 IEEE Workshop on Signal Processing Systems, pp. 54 –63, 1999.

J.M. Jou, P.-Y. Chen, Y.-H. Shiau, and M.-S. Liang “A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform,” Proc. of Asia and South Pacific Design Automation Conference, pp.205-208, 1999.

R.-D. Chen, J.M. Jou, and Y.-H. Shiau “Hazard-Free Synthesis and Decomposition of Asynchronous Circuits,” Proc. of Asia and South Pacific Design Automation Conference, pp.185-188, 1999.

J.M. Jou and P.-Y. Chen "An Adaptive Arithmetic Coding Method Using Fuzzy Logic and Gray Theory," Proc. of IEEE Inter. Symposium on Circuits and Systems, 1998.

J.M. Jou, S.C. Chen, and C.-L. Wang "Fast Delay-Dependent Power Estimation of Large Combinational Circuits," Proc. of IEEE Inter. Symposium on Circuits and Systems, 1998.

J.M. Jou and P.-Y. Chen "A Data Compression Method Using Adaptive Binary Arithmetic coding and Fuzzy Logic," Proc. of The 3-rd Asian Fuzzy Systems Symposium, pp.756-761, 1998.

J.M. Jou, P.-Y. Chen, and J.-M. Sun "The Novel Fuzzy Search Algorithm for Block Motion Estimation," Proc. of The 3-rd Asian Fuzzy Systems Symposium, pp.750-755, 1998.

S.-C. Chen and J.M. Jou, "Sequential Diagnostic Fault Simulation for Synchronous Sequential Circuit," Integration, The VLSI Journal, vol.23, pp.157-170, 1997.

Jer Min Jou, Y.-L. Lee, S.-S. Wu “Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2011

M.- C. Li and Jer Min Jou “Hw/Sw and Drivers Co-design of an Embedded JPEG Image Coder” Proceedings of Workshop on Consumer Electronics, 2011

M.- C. Li and Jer Min Jou “Hw/Sw Co-design of a JPEG Coder with Efficient Data Transfer” in National Computer Symposium, 2011

Jer Min Jou, Yun-Lung Lee, and Sih-Sian Wu, "Design Space Exploration and Construction of an Arbiter Design Model", Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2009

Sheng-Yun Zhang, Jer Min Jou, and Guan-Shiue Wu, “A Virtual Machine-based Platform Design for SoC/NoC Verification/Simulation” Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008

Yen-Yu Chen, Jer Min Jou, Yun-Long Lee, and Guan-Shiue Wu, “A High-Speed and Decentralized Arbiter Design for NoC”, Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008

Yun-Lung Lee, Sheau-Fang Lei, and Yen-Yu Chen, “A Fast Centralized Arbiter Design for NoC”, Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008

Yun-Lung Lee, Jer Min Jou, Tsung-Tan Shin, “A Reconfigurable Floating-Point Co-processor Design”, Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008

, “HW/SW Co-Design of a Multi-Threaded Virtual Machine for a Scalable NoC Platform”, Proceedings of the 2007 VLSI Design/CAD Symposium, 8-12, August, 2007.

Shih-Hsun Hsu, Yu-Xuan Lin, Jer-Min Jou and Yuan-Long Jeang, “A Reconfigurable NoC Router with AMBA-based Network Interface”, Proceedings of the 2006 VLSI Design/CAD Symposium, 8-11, August, 2006.

Chien-Ming Sun, Chen-Yen Lin, and Jer-Min Jou, “Design of a Novel Reconfigurable Arithmetic Unit Array Architecture”, Proceedings of the 2006 VLSI Design/CAD Symposium, 8-11, August, 2006.

Bu-Ren Zheng, Chien-Fu Huang and Jer-Min Jou, “Reconfigurable Scan Chain Design for Delay Fault Testing”, Proceedings of the 2006 VLSI Design/CAD Symposium, 8-11, August, 2006.

Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee and Chien-Ming Sun, “Design of a New Pipelined Router for NoC”, 2005 National Computer Symposium, December, 15 – 16, 2005.

Zi-Lun Wang, Jer-Min Jou, Shih-Hsun Hsu , Ming-Chao Lee, Chien-Ming Sun and Hung-Wei Yang, “Design of a Low Power ASIP for Network-on-Chip Routing”, 2005 Workshop on Consumer Electronics and Signal Processing, November, 17 – 18, 2005.

Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee, Chien-Ming Sun and Hung-Wei Yang, “Design of a New Pipelined Router for NoC”, 2005 Workshop on Consumer Electronics and Signal Processing, November, 17 – 18, 2005.

Hao-I Yang, Jer-Min Jou, Chin-Ming Sun, Shih-Hsun Hsu, Ming-Chao Lee , “Design of A Run-time Reconfigurable Superscalar System Platform For NoC,” Proceedings of the VLSI Design/CAD Symposium, 2005.

Shih-Lun Chen, Jer-Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Haoi Yang, Hong-Yi Su,"Reconfigurable Processor Core Design for Network-on-a-Chip," ICS 2004, 2004.

Chien-Ming Sun, Jer Min Jou, Hong-Yi Su, Ye-Xuan Yan, and Haoi Yang, "Design of a Multi-tile Reconfigurable Platform for DSP Applications," WCE2004, 2004.

Shih-Hsun Hsu, Jer-Min Jou, and Yuan-Chin Wu, "New Routing Algorithms and Router Architecture Design for NoC," Proceedings of the 2004 VLSI Design/CAD Symposium, 2004.

Ye-Xuan Yan, Jer-Min Jou, Yuan-Chin Wu, and Shih-Hsun Hsu, "A Field Programmable DSP PlatformDesign," Proceedings of the 2004 VLSI Design/CAD Symposium, 2004.

Jer-Min Jou, "Reconfigurable SoC Architectures," Proceedings of the 2003 VLSI Design/CAD Symposium, 2003.

Jun-Sheng Zheng, Jer-Min Jou and Yeu-Horng Shiau, “ Hierarchical Interface Design Methodology : Using Real -Time MPEG 1Audio layer3 codec as a case,” Proceedings of the 2002 VLSI Design/CADSymposium, pp.301-304, 2002.

Tzeng-Yi Lin, Jer-Min Jou, Shiann-Rong Kuang and Yeu-Horng Shiau, “Hardware Implementation of Network Layer Protocol Transform Between IP and ATM Applied in Edge Router,” Proceedings of the 2002 VLSI Design/CAD Symposium, pp.322-325, 2002.

Yu-Chia Chen, Yeu-Horng Shiau, Shiann-Rong Kuang, and Jer-Min Jou, “Design of An Integrated MAC IP for IEEE 1394 and Ethernet,” Proceedings of the 2002 VLSI Design/CAD Symposium, pp.326-329, 2002.

Kuang-Li Wu, Jer-Min Jou, and Yeu-Horng Shiau, “Bus Wrapper Design Methodology in the SoC,”Proceedings of the 2002 VLSI Design/CAD Symposium, pp. 524-527, 2002.

周哲民, 蕭宇宏, 張博皓, 陳昱嘉, “家用網路影像傳輸IP及單晶片系統之設計與研製, ” Proceedings of Workshop on Consumer Electronics, 2002.

Y.-H. Shiau, Y.-T. Hu, S.-R. Kuang, J. M. Jou, "System Design of JPEG2000 Still Image Compression Coder," The 12th VLSI Design/CAD Symposium, pp. B2-2, 2001.

Y.-H. Shiau, P.-H. Chang, S.-R. Kuang, and J. M. Jou, "Hardware Software Co-design and Implementation of Wavelet-based Video Compression System, " The 12th VLSI Design/CAD Symposium, pp. B2-4, 2001.

K.-M. Wu and J. M. Jou, "A Hierarchical Interface Design Methodology and Models for SoC IP Integration," The 12th VLSI Design/CAD Symposium, pp. B2-8, 2001.

W.-S. Huang, J. M. Jou, Y.-H. Shiau, "Efficient Modular Hardware Design For Continuous Speech Recognition," The 12th VLSI Design/CAD Symposium, pp. C3-1, 2001.

C.-J. Huang, Y.-H. Shiau, and J. M. Jou, "A High Speed and Area-Efficient Survivor Path Architecture for HMM Based Speech Recognition," The 11th VLSI Design/CAD Symposium, pp. 49-52, 2000.

J.M. Jou, Y.-H. Shiau, and Y.-S. Hsieh, “The Chip Implementation and HW/SW Co-simulation of A DWT-based Coding System”, The 11th VLSI Design/CAD Symposium, pp. 45-48. 2000.

C.-C. Liu, Y.-H. Shiau, and J.M. Jou, “Design and implement of a progressive image coding chip based on the lifted wavelet transform”, The 11th VLSI Design/CAD Symposium, pp. 49-52. 2000.

J.M. Jou, S.R. Kuang, Y.-H. Shiace, and J.P. Chang "Dynamic Pipelined Architecture for Fuzzy Color Correction," Proc. of The 9th VLSI Design/CAD Symposium, pp.15-18, 1998.

R.-D. Chen and J.M. Jou, "STG-Level Synthesis and Decomposition of Speed-Independent Circuits," Proc. of the 9th VLSI Design/CAD Symposium, pp.27-30, 1998.

R.-D. Chen, C.-C Wu and J.M. Jou, "Design and Implementation of an Asynchronous Adaptive Echo Chancellor," Proc. of the 9th VLSI Design/CAD Symposium, pp.457-460, 1998.

P.-Y. Chen, M.S. Liang, and J.M. Jou, "Design of A Scalable Pipelined Architecture For 2-D Wavelet Transform, " Proc. of the 9th VLSI Design/CAD Symposium, pp.305-308, 1998.

周哲民???et. al.“高時效動態管線化電路設計法”美國專利,?2003.

其他協助產業技術發展之具體績效?:??95年協助科學園區智邦公司研發無損壓縮方法.

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