NCKU EE 教師個人頁面
English Version
周哲民 教授
地址
奇美系館6樓95601室
TEL
+886-6-2757575 ext.62365
實驗室網站連結
學經歷
學歷
1987
國立成功大學博士
1983
國立成功大學碩士
1981
國立成功大學學士
經歷
1983-1989
國立成功大學電機系講師
1988-1989
陸軍總部資訊室系統分析
1984-1984
工研院電子所數位系統部研究
研究領域
  • 人工智慧研究與其相關晶片設計
  • 深度捲積神經網路硬體設計
  • 超大型積體電路電腦輔助設計
  • 應用導向IC設計
  • 系統單晶片設計
  • 網路系統單晶片設計
著作
期刊論文( Journal )
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  1. Jer Min Jou, Yun-Lung Lee, Sih-Sian Wu, "Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis" ,in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD).
  2. Jer-Min Jou and Yun-Lung Lee, "A Optimal Round-Robin Arbiter Design for NoC", in the Journal of Information Science and Engineering 2010
  3. Yun-Lung Lee, Yung-Chao Chen, Jer-Min Jou, and Shiann-Rong Kuang,"HW/SW Co-Design of a Multi-Threaded Java Virtual Machine", International Journal of Electrical Engineering, 2008
  4. Jer-Min Jou, Chien-Ming Sun, Chen-Yen Lin, Yun-Lung Lee, Yuan-Long Jeang, “Design of a Novel Reconfigurable Arithmetic Unit Array Architecture,” to be published in the International Journal of Electrical Engineering, 2007.
  5. Yuan-Long Jeang, Jer-Min Jou, Win-Hsien Huang, “A Binary Tree Based Methodology for Designing an Application Specific Network-on-Chip (ASNOC)”, IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, 2006.
  6. Jer Min Jou, Chien-Ming Sun, Hong-Yi Su, Shih-Hsun Hsu and Ming-Chao Lee “Run-Time Multi-tile Reconfigurable Hardware Platform Design for Multimedia Applications,” The invited journal papers of Avtometriya, Russia, 2005.
  7. Y.-H. Shiau, J.M. Jou, and C.-C. Liu, “Efficient Architectures for the Biothogonal Wavelet Transform by Filter Bank and Lifting Scheme,” IEICE Transactions on Information and Systems, July, 2004.
  8. Y.-H. Shiau and J.M. Jou, "A High-Performance Tree-Block Pipelining Architecture for Separable 2-D Inverse Discrete Wavelet Transform," IEICE Transactions on Information and Systems, vol. E86-D, no. 10, pp. 1966-1975, 2003.
  9. J.M. Jou, S.R. Kuang, and Y.-H. Shiau "Dynamic Pipelined Architecture for Fuzzy Color Correction,"IEEE Trans. On VLSI, pp.924-928, 2003.
  10. R.-D. Chen and J.M. Jou, "STG-level decomposition and resynthesis of speed-independent circuits," IEEE Transactions on Circuits & Systems Part I, pp.1151-1163, Dec., 2002, USA.
  11. J.M. Jou, Y.-H. Shiau, P.-Y. Chen, and S.-R. Kuang, "A Low Cost Gray Prediction Search Chip for Motion Estimation," IEEE Transactions on Circuits & Systems Part I, pp. 928-928, July, 2002, USA.
  12. S.-R. Kuang, J.M. Jou, R.-D. Chen, Y.-H. Shiau, "Dynamic Pipeline Design of an Adaptive Binary Arithmetic Coder," IEEE Transactions on Circuits & Systems Part II, pp.813-825, Sept. 2001, USA.
  13. P.-Y. Chen and J.M. Jou, "An Efficient Block-Matching Algorithm Based on Fuzzy Reasoning," IEEE Trans. on System, Man, and Cybernetics, vol.31, no.2, pp.253-259, 2001, USA.
  14. J.M. Jou, P.-Y. Chen and S.-F. Yang, "An Adaptive Fuzzy Logic Controller: Its VLSI Architecture and Applications," IEEE Trans. on VLSI, vol. 8, no. 1, pp.52-60, Jan. 2000, USA.
  15. J.M. Jou and P.-Y. Chen "Adaptive Arithmetic Coding Using Fuzzy Reasoning and Gray Theory," International Journal for Fuzzy Sets and Systems, vol.114, no.2, pp.239-254, 2000.
  16. J.M. Jou, S.-R. Kuang, and R. D. Chen, “Design of Low-Error Fixed-Width Multipliers for DSP Applications,” IEEE Transactions on Circuits & Systems Part II, vol.46, no.6, pp.836-842, June 1999.
  17. J.M. Jou and P.-Y. Chen "A Fast and Efficient lossless Data Compression Method," IEEE Trans. On Communications, vol.47, no.9, pp.1278-1283, 1999.
  18. J.M. Jou, S.-R. Kuang and R. D. Chen "A New Efficient Fuzzy Algorithm for Color Correction," IEEE Trans. on Circuits & Systems Part I, vol. 46, no. 6, pp.773~775, 1999.
  19. P.-Y. Chen, and J.M. Jou "A Fast-Search Motion Estimation Method and its VLSI Architecture," IEEE Trans. On Circuits and Systems Part II, vol. 46, no. 9, pp.1233-1240, 1999.
  20. J.M. Jou, P.-Y. Chen, and J.-M. Sun "The Gray Prediction Search Algorithm for Block Motion Estimation," IEEE Transactions on Circuits & Systems for Video Technology, vol.9, no.6, pp.843-848, 1999, USA.
  21. S.-R. Kuang, J.M. Jou and Y.-L. Chen "The Design of an Adaptive On-Line Binary Arithmetic Coding Chip," IEEE Trans. on Circuits & Systems Part I, Vol.45, No.7, pp.693-706, 1998.
  22. S.-C. Chen and J.M. Jou, "Diagnostic Fault Simulation for Synchronous Sequential Circuit," IEEE Trans. on CAD, vol.17, no.3, pp.299-308, 1997.
  23. J.M. Jou and S.R. Kuang, "Design of a low-error fixed-width multiplier for DSP applications" Electronic Letters, vlo.33, no.19, pp.1597-1598, 1997.
會議論文( Conference )
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  1. Chun-Yu Chen, Lee Yun-Lung, and Jer Min Jou. "A Transaction-based Design Model and Its MPEG-2 Encoder Design" in International Computer Symposium(ICS), 2014
  2. Cheng-Hung Hsieh, Jer-Min Jou, "A Run-time Manager For Multithreading Of Multi-core Systems" in Interational Computer Symposium(ICS), 2014
  3. J.-H. Liao, Jer Min Jou, C.-H. Hsieh, and D.-Y. Lin : Hardware Acceleration Design for Embedded Operating System Scheduling, J.-S. Pan et al. (Eds): Advances in Intelligent Systems & Applications, Vol.2, SIST 21, pp. 759-767, 2012
  4. W.-H. Chang, Jer Min Jou, C.-H. Hsieh, and D.-Y. Lin : A Distributed Run-Time Dynamic Data Manager for Multi-core System Parallel Execution, J.-S. Pan et al. (Eds): Advances in Intelligent Systems & Applications, Vol.2, SIST 21, pp. 741-750, 2012.
  5. S. H., Jer Min Jou, C.-H. Hsieh, and D.-Y. Lin : Design of a Dynamic Parallel Execution Architecture for Multi-Core Systems, J.-S. Pan et al. (Eds): Advances in Intelligent Systems & Applications, Vol.2, SIST 21, pp. 731-740, 2012.
  6. Jer Min Jou, Sih-Sian Wu, Yun-Lung Lee, Cheng Chou, Yuan-Long Jeang, “New model-driven design and generation of multi-facet arbiters part I: From the design model to the architecture model”, Design Automation Conference (DAC), 2010 47th ACM/IEEE.
  7. Jer Min Jou, Yun-Lung Lee, Sih-Sian Wu, "Efficient design and generation of a multi-facet arbiter",Application Specific Processors (SASP), 2010 IEEE 8th Symposium on
  8. Yun-Lung Lee, Jer Min Jou and Yen-Yu Chen,"A High-Speed and Decentralized Arbiter Design for NoC", The 7th ACS/IEEE International Conference on Computer Systems and Applications 2009
  9. Jer Min Jou, Yun-Lung Lee, Ren-Der Chen, Sih-Sian Wu, Cheng Chou, and Yen-Yu Chen,"Design Space Exploration and Construction of an Arbiter Design Model", National Computer Symposium 2009
  10. Yun-Lung Lee, Jer Min Jou, ” Design of A Reconfigurable Floating-Point Unit”, International Computer Symposium, pp.294 ~ pp.298, ICS 2008
  11. Yun-Lung Lee, Jer Min Jou, Yen-Yu Chen, Sih-Sian Wu, “A Optimal Arbiter Design for NoC”, International Computer Symposium, pp.288 ~ pp.293, ICS 2008
  12. Yun-Lung Lee, Jun-Wei Yang, and Jer Min Jou, "Design of a Distributed JPEG Encoder on a Scalable NoC Platform", VLSI-DAT,2008
  13. Jer Min Jou, Y.-L. Lee, and C.-Y. Lin, “A Novel Reconfigurable Computation Unit for DSP Applications”,The IEEE Computer Society Annual Symposium on VLSI, 2007
  14. Shih-Hsun Hsu, Yu-Xuan Lin and Jer-Min Jou, “Design of a Dual-Mode NoC Router Integrated with Network Interface for AMBA-based IPs”, Asian Solid-State Circuits Conference (A-SSCC) 2006, 13-15, November, 2006.
  15. Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee, Chien-Ming Sun, “An Effieient NoC Pipelined Router Design”, International Conference on Computer & Communication Engineering (ICCCE '06), 9-11, May, 2006.
  16. Shih-Hsun Hsu, Zi-Lun Wang, Jer-Min Jou, Ming-Chao Lee, Chien-Ming Sun, “A Low Power Routing ASIP for NoC”, International Conference on Computer & Communication Engineering (ICCCE '06), 9-11, May, 2006.
  17. Jer Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Ming-Chao Lee, Ye-Xuan Yan, Hong-Yi Su, and Haoi Yang, “A Multi-tile Reconfigurable Platform Design for DSP Applications,” ACIT-SIP 2005, Novosibirsk, Russia, June 20-24, 2005.
  18. Shih-Lun Chen, Jer-Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Haoi Yang, Hong-Yi Su,"Reconfigurable Processor Core Design for Network-on-a-Chip," International Computer Symposium, 2004.
  19. J. M. Jou et. al., "System Design of NoC”, Proceedings of the 2003 MiddleEast Circuits & Systems Conference, 2003.
  20. Kuang-Li Wu, Jer-Min Jou, Yeu-Horng Shiau, and Ren-Der Chen, “Bus Wrapper Design Methodology in SoC, ” Proceedings of 2002 International Computer Symposium, 2002.
  21. Yeu-Horng Shiau, Jer-Min Jou and Tsung-Chih Wang, “Design of Modular Scalable HMM-based Continuous Speech Recognition / Convolutional Decoder IP, ” Proceedings of 2002 International Computer Symposium, 2002.
  22. J. M. Jou, S.-R. Kuang, and K.-M. Wu, "A Hierarchical Interface Design Methodology And Models For SoC IP Integration," IEEE International Symposium On Circuits and Systems, pp.360 –363, 2002.
  23. Jer Min Jou, Yeu Horng Shiau and Bu Ren Zheng, “A novel motion estimation algorithm and its VLSI architecture,” Proceedings of 2002 IEEE Asia-Pacific Conference on ASIC, pp. 241-244, 2002.
  24. J. M. Jou, Y.-H. Shiau, and C.-C. Liu, "Efficient VLSI Architectures for the Biorthogonal Wavelet Transform by Filter Bank and Lifting Scheme," IEEE International Symposium On Circuits and Systems, pp. 529-533, 2001.
  25. Y.-H. Shiau and J.M. Jou, “A tree-block Scheduling Architecture for Separable 2-D Inverse Discrete Wavelet Transform”, International Computer Symposium, Workshop on Image Processing and Pattern Recognition, 2000.
  26. J.M. Jou, P.-Y. Chen, Y.-H. Shiau, and J.-M. Sun, “A grey prediction motion estimator for digital image processing”, The 6th IEEE International Conference on Electronics, Circuits and Systems, Proceedings of ICECS '99, Vol. 2, pp. 701-704, 1999.
  27. J.M. Jou, S.-R. Kuang and Y.-H. Shiau “A New Pipelined Architecture for Fuzzy Color Correction,” Proc. of Asia and South Pacific Design Automation Conference, pp.209-212, 1999.
  28. Y.-H. Shiau, P.-Y. Chen, and J. M. Jou, “A gray-based block-matching algorithm and its VLSI architecture”, 1999 IEEE Workshop on Signal Processing Systems, pp. 54 –63, 1999.
  29. J.M. Jou, P.-Y. Chen, Y.-H. Shiau, and M.-S. Liang “A Scalable Pipelined Architecture for Separable 2-D Discrete Wavelet Transform,” Proc. of Asia and South Pacific Design Automation Conference, pp.205-208, 1999.
  30. R.-D. Chen, J.M. Jou, and Y.-H. Shiau “Hazard-Free Synthesis and Decomposition of Asynchronous Circuits,” Proc. of Asia and South Pacific Design Automation Conference, pp.185-188, 1999.
  31. J.M. Jou and P.-Y. Chen "An Adaptive Arithmetic Coding Method Using Fuzzy Logic and Gray Theory," Proc. of IEEE Inter. Symposium on Circuits and Systems, 1998.
  32. J.M. Jou, S.C. Chen, and C.-L. Wang "Fast Delay-Dependent Power Estimation of Large Combinational Circuits," Proc. of IEEE Inter. Symposium on Circuits and Systems, 1998.
  33. J.M. Jou and P.-Y. Chen "A Data Compression Method Using Adaptive Binary Arithmetic coding and Fuzzy Logic," Proc. of The 3-rd Asian Fuzzy Systems Symposium, pp.756-761, 1998.
  34. J.M. Jou, P.-Y. Chen, and J.-M. Sun "The Novel Fuzzy Search Algorithm for Block Motion Estimation," Proc. of The 3-rd Asian Fuzzy Systems Symposium, pp.750-755, 1998.
  35. S.-C. Chen and J.M. Jou, "Sequential Diagnostic Fault Simulation for Synchronous Sequential Circuit," Integration, The VLSI Journal, vol.23, pp.157-170, 1997.
  36. Jer Min Jou, Y.-L. Lee, S.-S. Wu “Model-Driven Design and Generation of New Multi-Facet Arbiters: From the Design Model to the Hardware Synthesis” in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2011
  37. M.- C. Li and Jer Min Jou “Hw/Sw and Drivers Co-design of an Embedded JPEG Image Coder” Proceedings of Workshop on Consumer Electronics, 2011
  38. M.- C. Li and Jer Min Jou “Hw/Sw Co-design of a JPEG Coder with Efficient Data Transfer” in National Computer Symposium, 2011
  39. Jer Min Jou, Yun-Lung Lee, and Sih-Sian Wu, "Design Space Exploration and Construction of an Arbiter Design Model", Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2009
  40. Sheng-Yun Zhang, Jer Min Jou, and Guan-Shiue Wu, “A Virtual Machine-based Platform Design for SoC/NoC Verification/Simulation” Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008
  41. Yen-Yu Chen, Jer Min Jou, Yun-Long Lee, and Guan-Shiue Wu, “A High-Speed and Decentralized Arbiter Design for NoC”, Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008
  42. Yun-Lung Lee, Sheau-Fang Lei, and Yen-Yu Chen, “A Fast Centralized Arbiter Design for NoC”, Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008
  43. Yun-Lung Lee, Jer Min Jou, Tsung-Tan Shin, “A Reconfigurable Floating-Point Co-processor Design”, Proceedings of the 2008 VLSI Design/CAD Symposium, August, 2008
  44. , “HW/SW Co-Design of a Multi-Threaded Virtual Machine for a Scalable NoC Platform”, Proceedings of the 2007 VLSI Design/CAD Symposium, 8-12, August, 2007.
  45. Shih-Hsun Hsu, Yu-Xuan Lin, Jer-Min Jou and Yuan-Long Jeang, “A Reconfigurable NoC Router with AMBA-based Network Interface”, Proceedings of the 2006 VLSI Design/CAD Symposium, 8-11, August, 2006.
  46. Chien-Ming Sun, Chen-Yen Lin, and Jer-Min Jou, “Design of a Novel Reconfigurable Arithmetic Unit Array Architecture”, Proceedings of the 2006 VLSI Design/CAD Symposium, 8-11, August, 2006.
  47. Bu-Ren Zheng, Chien-Fu Huang and Jer-Min Jou, “Reconfigurable Scan Chain Design for Delay Fault Testing”, Proceedings of the 2006 VLSI Design/CAD Symposium, 8-11, August, 2006.
  48. Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee and Chien-Ming Sun, “Design of a New Pipelined Router for NoC”, 2005 National Computer Symposium, December, 15 – 16, 2005.
  49. Zi-Lun Wang, Jer-Min Jou, Shih-Hsun Hsu , Ming-Chao Lee, Chien-Ming Sun and Hung-Wei Yang, “Design of a Low Power ASIP for Network-on-Chip Routing”, 2005 Workshop on Consumer Electronics and Signal Processing, November, 17 – 18, 2005.
  50. Shih-Hsun Hsu, Jer-Min Jou, Ming-Chao Lee, Chien-Ming Sun and Hung-Wei Yang, “Design of a New Pipelined Router for NoC”, 2005 Workshop on Consumer Electronics and Signal Processing, November, 17 – 18, 2005.
  51. Hao-I Yang, Jer-Min Jou, Chin-Ming Sun, Shih-Hsun Hsu, Ming-Chao Lee , “Design of A Run-time Reconfigurable Superscalar System Platform For NoC,” Proceedings of the VLSI Design/CAD Symposium, 2005.
  52. Shih-Lun Chen, Jer-Min Jou, Chien-Ming Sun, Yuan-Chin Wu, Haoi Yang, Hong-Yi Su,"Reconfigurable Processor Core Design for Network-on-a-Chip," ICS 2004, 2004.
  53. Chien-Ming Sun, Jer Min Jou, Hong-Yi Su, Ye-Xuan Yan, and Haoi Yang, "Design of a Multi-tile Reconfigurable Platform for DSP Applications," WCE2004, 2004.
  54. Shih-Hsun Hsu, Jer-Min Jou, and Yuan-Chin Wu, "New Routing Algorithms and Router Architecture Design for NoC," Proceedings of the 2004 VLSI Design/CAD Symposium, 2004.
  55. Ye-Xuan Yan, Jer-Min Jou, Yuan-Chin Wu, and Shih-Hsun Hsu, "A Field Programmable DSP PlatformDesign," Proceedings of the 2004 VLSI Design/CAD Symposium, 2004.
  56. Jer-Min Jou, "Reconfigurable SoC Architectures," Proceedings of the 2003 VLSI Design/CAD Symposium, 2003.
  57. Jun-Sheng Zheng, Jer-Min Jou and Yeu-Horng Shiau, “ Hierarchical Interface Design Methodology : Using Real -Time MPEG 1Audio layer3 codec as a case,” Proceedings of the 2002 VLSI Design/CADSymposium, pp.301-304, 2002.
  58. Tzeng-Yi Lin, Jer-Min Jou, Shiann-Rong Kuang and Yeu-Horng Shiau, “Hardware Implementation of Network Layer Protocol Transform Between IP and ATM Applied in Edge Router,” Proceedings of the 2002 VLSI Design/CAD Symposium, pp.322-325, 2002.
  59. Yu-Chia Chen, Yeu-Horng Shiau, Shiann-Rong Kuang, and Jer-Min Jou, “Design of An Integrated MAC IP for IEEE 1394 and Ethernet,” Proceedings of the 2002 VLSI Design/CAD Symposium, pp.326-329, 2002.
  60. Kuang-Li Wu, Jer-Min Jou, and Yeu-Horng Shiau, “Bus Wrapper Design Methodology in the SoC,”Proceedings of the 2002 VLSI Design/CAD Symposium, pp. 524-527, 2002.
  61. 周哲民, 蕭宇宏, 張博皓, 陳昱嘉, “家用網路影像傳輸IP及單晶片系統之設計與研製, ” Proceedings of Workshop on Consumer Electronics, 2002.
  62. Y.-H. Shiau, Y.-T. Hu, S.-R. Kuang, J. M. Jou, "System Design of JPEG2000 Still Image Compression Coder," The 12th VLSI Design/CAD Symposium, pp. B2-2, 2001.
  63. Y.-H. Shiau, P.-H. Chang, S.-R. Kuang, and J. M. Jou, "Hardware Software Co-design and Implementation of Wavelet-based Video Compression System, " The 12th VLSI Design/CAD Symposium, pp. B2-4, 2001.
  64. K.-M. Wu and J. M. Jou, "A Hierarchical Interface Design Methodology and Models for SoC IP Integration," The 12th VLSI Design/CAD Symposium, pp. B2-8, 2001.
  65. W.-S. Huang, J. M. Jou, Y.-H. Shiau, "Efficient Modular Hardware Design For Continuous Speech Recognition," The 12th VLSI Design/CAD Symposium, pp. C3-1, 2001.
  66. C.-J. Huang, Y.-H. Shiau, and J. M. Jou, "A High Speed and Area-Efficient Survivor Path Architecture for HMM Based Speech Recognition," The 11th VLSI Design/CAD Symposium, pp. 49-52, 2000.
  67. J.M. Jou, Y.-H. Shiau, and Y.-S. Hsieh, “The Chip Implementation and HW/SW Co-simulation of A DWT-based Coding System”, The 11th VLSI Design/CAD Symposium, pp. 45-48. 2000.
  68. C.-C. Liu, Y.-H. Shiau, and J.M. Jou, “Design and implement of a progressive image coding chip based on the lifted wavelet transform”, The 11th VLSI Design/CAD Symposium, pp. 49-52. 2000.
  69. J.M. Jou, S.R. Kuang, Y.-H. Shiace, and J.P. Chang "Dynamic Pipelined Architecture for Fuzzy Color Correction," Proc. of The 9th VLSI Design/CAD Symposium, pp.15-18, 1998.
  70. R.-D. Chen and J.M. Jou, "STG-Level Synthesis and Decomposition of Speed-Independent Circuits," Proc. of the 9th VLSI Design/CAD Symposium, pp.27-30, 1998.
  71. R.-D. Chen, C.-C Wu and J.M. Jou, "Design and Implementation of an Asynchronous Adaptive Echo Chancellor," Proc. of the 9th VLSI Design/CAD Symposium, pp.457-460, 1998.
  72. P.-Y. Chen, M.S. Liang, and J.M. Jou, "Design of A Scalable Pipelined Architecture For 2-D Wavelet Transform, " Proc. of the 9th VLSI Design/CAD Symposium, pp.305-308, 1998.
專利
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  1. 周哲民,鄺獻榮,“低誤差固定寬度(Fixed-width)二補數平行乘法器” 中華民國專利, no.117044, 2000。
  2. 周哲民,鄺獻榮,“高時效動態管線化電路設計法”中華民國專利,?no.137795,?2001.
  3. 周哲民,鄺獻榮,“高時效動態管線化電路設計法”美國專利2002.
  4. 周哲民???et. al.“高時效動態管線化電路設計法”美國專利,?2003.
  5. 其他協助產業技術發展之具體績效?:??95年協助科學園區智邦公司研發無損壓縮方法.
其他
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  1. 用於AI機器學習之動態迴圈運算器設計(國科會,2017)
  2. 粗粒度混合流之動態評估管控器設計與實作(國科會,2016)
  3. 事務式動態適應控制器晶片設計與實作(國科會,2015)
  4. 多核心之動態任務萃取器的設計(I)(國科會,2014)
  5. 解耦式多核平行運算平台之設計(國科會, 2013)
  6. 用於多核多執行緒並行執行之執行期動態資料管控器((國科會,2011)
  7. 多面向仲裁器之模型驅動平台式設計與實作(國科會,2010)
  8. 用於低功浩和高性能的MPSoCs的動態硬體排程器之研究與設計(國科會,2009)
  9. 使用虛擬化技術研發之多形多 嵌入式硬體平台(國科會, 2008)
  10. 一個基於單晶片網路之多態串流軟硬體協同設計平台的設計和製作-單晶片網路(NoC)多態串流平台之系統架構與其多態串流處理單元的設計和製作(國科會, 2007)
  11. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(III) (總計畫) (國科會, 2006)
  12. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(III) (子計畫二): 低功率可重置嵌入式處理器
  13. 用於多媒體資料處理之可重置低功率NoC平台的設計與實現(I) (總計畫) (國科會, 2006)
  14. 用於多媒體資料處理之可重置低功率NoC平台的設計與實現(I) (子計畫六): NoC平台之可重置低功率路由器的設計(I) (國科會, 2005)
  15. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(II) (總計畫) (國科會, 2005)
  16. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(II) (子計畫二): 低功率可重置嵌入式處理器矽核研製(II) (國科會, 2005)
  17. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(I) (總計畫) (國科會, 2004)
  18. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(I) (子計畫二): 低功率可重置嵌入式處理器矽核研製(I) (國科會, 2004)
  19. 適應性單晶片網路系統平台之適應性非集中化通訊介面與網路管控矽核研發與設計(I) (國科會, 2003)
  20. 設計一個系統單晶片網路-以視訊串流單晶片系統整合為標的 (國科會, 2002)
  21. SoC階層化介面電路設計法則與模型的研發-- 以MP3為設計標的 (國科會, 2001)
  22. 家用網路影像傳輸IP及單晶片系統之設計與研製(二) (國科會, 2001)
  23. 一個適用於JPEG-2000之快速有效量化與熵編碼器的研究與實現 (國科會, 2000)
  24. 家用網路影像傳輸IP及單晶片系統之設計與研製(一) (國科會, 2000)
  25. 用於互動式電視之非同步可階式多重解析度編碼系統 (國科會, 1999)
  26. ─用於互動式電視中的可階式非同步濾波器組之VLSI設計 (國科會, 1998)
研究計劃
  1. 用於AI機器學習之動態迴圈運算器設計(國科會,2017)
  2. 粗粒度混合流之動態評估管控器設計與實作(國科會,2016)
  3. 事務式動態適應控制器晶片設計與實作(國科會,2015)
  4. 多核心之動態任務萃取器的設計(I)(國科會,2014)
  5. 解耦式多核平行運算平台之設計(國科會, 2013)
  6. 用於多核多執行緒並行執行之執行期動態資料管控器((國科會,2011)
  7. 多面向仲裁器之模型驅動平台式設計與實作(國科會,2010)
  8. 用於低功浩和高性能的MPSoCs的動態硬體排程器之研究與設計(國科會,2009)
  9. 使用虛擬化技術研發之多形多 嵌入式硬體平台(國科會, 2008)
  10. 一個基於單晶片網路之多態串流軟硬體協同設計平台的設計和製作-單晶片網路(NoC)多態串流平台之系統架構與其多態串流處理單元的設計和製作(國科會, 2007)
  11. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(III) (總計畫) (國科會, 2006)
  12. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(III) (子計畫二): 低功率可重置嵌入式處理器
  13. 用於多媒體資料處理之可重置低功率NoC平台的設計與實現(I) (總計畫) (國科會, 2006)
  14. 用於多媒體資料處理之可重置低功率NoC平台的設計與實現(I) (子計畫六): NoC平台之可重置低功率路由器的設計(I) (國科會, 2005)
  15. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(II) (總計畫) (國科會, 2005)
  16. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(II) (子計畫二): 低功率可重置嵌入式處理器矽核研製(II) (國科會, 2005)
  17. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(I) (總計畫) (國科會, 2004)
  18. 用於嵌入式多媒體並行處理之低功率可重置式處理器矽核之研製(I) (子計畫二): 低功率可重置嵌入式處理器矽核研製(I) (國科會, 2004)
  19. 適應性單晶片網路系統平台之適應性非集中化通訊介面與網路管控矽核研發與設計(I) (國科會, 2003)
  20. 設計一個系統單晶片網路-以視訊串流單晶片系統整合為標的 (國科會, 2002)
  21. SoC階層化介面電路設計法則與模型的研發-- 以MP3為設計標的 (國科會, 2001)
  22. 家用網路影像傳輸IP及單晶片系統之設計與研製(二) (國科會, 2001)
  23. 一個適用於JPEG-2000之快速有效量化與熵編碼器的研究與實現 (國科會, 2000)
  24. 家用網路影像傳輸IP及單晶片系統之設計與研製(一) (國科會, 2000)
  25. 用於互動式電視之非同步可階式多重解析度編碼系統 (國科會, 1999)
  26. ─用於互動式電視中的可階式非同步濾波器組之VLSI設計 (國科會, 1998)
指導學生
本學年度 實驗室成員
碩士班
胡雨霖
廖祥宇
陳聖諺
胡連鈞
陳建彰
謝明翰
劉邦彥
郭珍瑋
林志泓
蘇敬傑
歐潤陽
張育倫
黃聖傑
王鈺堡
黃崇晉
葉育辰
已畢業學生
博士班
陳順治   鄺獻榮   陳仁德   陳培殷   蕭宇宏   孫建明   許世勳   李昀隆
碩士班
105
陳柏憲   陳善文
104
黃喬楷   黃翔   陳佑銓   徐子傑
102
謝政宏   林鼎原   張力升   林孟諭
101
蔡銘軒   黃致穎   林宏達   陳俊諭
100
黃詳   張駿豪   張文賢   廖健合   吳思憲
99
施廷憲   謝豐旭   許維哲   李明峻
98
陳彥瑜
97
吳冠學   廖英智   曾政傑
96
張勝雲   陳泳超   劉立林   鐘旗鴻   辛宗潭   楊竣崴   陳仕彬
95
林辰諺   楊宏偉   林郁軒   黃建輔   黃國惟   王長河
94
蘇弘毅   楊皓義   李智偉   王子綸   郭瑞宏
93
許世勳   吳源晉   邱庭鈺   顏業烜   陳世綸
92
林士生   林仁興   黃昭欽   涂義昇   許毓霖
91
陳昱嘉   吳光立   鄭君聖   王聰智   林增益
90
張博皓   胡毓宗   吳光明   黃文信
特殊榮譽
  1. 1987美國積體電路電腦輔助會議最佳論文獎 
  2. 指導大學生參加全國大學論文比賽獲特優(一次)
  3. 指導大學生參加全校論文比賽獲特優(二次) 
  4. 1993 中國電機工程學會青年論文獎第三名
  5. 2001 中國電機工程學會青年論文獎第一名
  6. 87年博士班研究生鄺獻榮榮獲宏碁龍騰博士論文最優獎
  7. 88年博士班研究生陳培殷榮獲宏碁龍騰博士論文佳作獎
  8. 89年碩士班研究生黃俊仁榮獲全國微電腦硬體設計競賽優等獎
  9. 90年碩士班研究生張博皓、吳光明、黃文信、陳昱嘉榮獲旺宏金矽獎第一屆半導體設計與應用大賽優勝獎
  10. 90年碩士班研究生張博皓榮獲中國電機工程學會青年論文獎第一名
  11. 90年碩士班研究生張博皓榮獲教育部大學院校矽智產IC設計FPGA組優勝獎
  12. 90年碩士班研究生胡毓宗榮獲教育部大學院校矽智產IC設計FPGA組佳作獎
  13. 90年碩士班研究生吳光明榮獲教育部大學院校矽智產IC設計FPGA組優勝及Soft IP組佳作獎
  14. 91年碩士班研究生鄭君聖榮獲教育部大學院校矽智產IC設計FPGA組佳作獎
  15. 92年博士班研究生陳仁德榮獲九十一學年度大學校院積體電路電腦輔助設計軟體製作競賽不定題組佳作獎
  16. 92年大學部指導學生楊皓義榮獲九十一學年度成大工學院學生論文創意競賽第二名
  17. 指導大學部學生參加 94全國大學論文比賽獲佳作獎
  18. 指導大學部學生參加 94全校論文比賽獲第三名獎
  19. 研發低功耗路由器ASIP榮獲2005年民生電子暨信號處理研討會最佳論文獎
  20. 2006年中華民國電腦學會優良論文佳作獎。
  21. 2008 International Computer Symposium, ICS, 最佳論文獎
  22. 2010榮獲思源EDA獎
  23. 2014 International Computer Symposium, ICS, 最佳論文獎
  24. 2015 Editorial board member of the International Journal Parallel and Distributed Computing and Networks
  25. 2016 Editorial board member of the International Journal Parallel and Distributed Computing and Networks
  26. 2017 Workshop on Consumer Electronics, WCE, 最佳論文獎