NCKU EE 教師個人頁面
English Version
陳中和 教授
地址
電機系館6樓92625室
TEL
+886-6-2757575 ext.62394
實驗室網站連結
計算機架構與系統實驗室
(R92617/ext.62400-1722)
學經歷
學歷
1993
華盛頓大學電機博士
1989
密蘇里-羅拉大學電機碩士
1983
國立台北工專
經歷
研究領域
  • 計算機架構
  • 多重處理器系統 
  • SoC系統整合
  • VLSI 晶片設計
  • 資料網路   
  • 微算機系統設計
  • 容錯處理系統 
著作
期刊論文( Journal )
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  1. En-Hao Chang, Chen-Chieh Wang, Chien-Te Liu, Kuan-Chung Chen and Chung-Ho Chen, Virtualization Technology for TCP/IP Offload Engine, IEEE Transactions on Cloud Computing, Vol. 2, No. 2, April-June 2014. (SCI, EI)
  2. Chen-Chieh Wang and Chung-Ho Chen,A System‐Level Network Virtual Platform for IPsec Processor Development, IEICE Transactions on Information and Systems, Vol.E96-D, No.5, pp.1095-1104, May 2013. (SCI, EI)
  3. Yi-Ying Tsai and Chung-Ho Chen,Energy-efficient Trace Reuse Cache for Embedded Processor,IEEE Transactions on Very Large Scale Integration Systems,Vol. 19, No. 9, pp. 1681-1694, September 2011. (SCI, EI)
  4. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,Effective Hybrid Test Program Development for Software-Based Self-Testing of Pipeline Processor Cores,IEEE Transactions on Very Large Scale Integration Systems,Vol. 19, No. 3, pp. 516-520, March 2011. (SCI, EI)
  5. Wei-Cheng Lin and Chung-Ho Chen,Frame Buffer Access Reduction for MPEG Video Decoder,IEEE Transactions on Circuits and Systems for Video Technology,Vol. 18, No. 10, pp. 1452-1456, October 2008. (SCI, EI)
  6. Chung-Ming Chen and Chung-Ho Chen,Configurable VLSI Architecture for Deblocking Filter in H.264/AVC,IEEE Transactions on Very Large Scale Integration Systems,Vol. 16, No. 8, pp. 1072-1082, August 2008. (SCI, EI)
  7. Chung-Ho Chen and Kuo-Su Hsiao,Scalable Dynamic Instruction Scheduler through Wakeup Spatial Locality,IEEE Transactions on Computers,Vol. 56, No. 11, pp. 1534-1548, November 2007. (SCI, EI)
  8. Chung-Ho Chen, Chih-Kai Wei, Tai-Hua Lu, and Hsun-Wei Gao,Software-Based Self-Testing with Multiple-Level Abstractions for Soft Processor Cores,IEEE Transactions on Very Large Scale Integration Systems,Vol. 15, No. 5, pp. 505-517, May 2007. (SCI, EI)
  9. Kuo-Su Hsiao and Chung-Ho Chen,Wake-Up Logic Optimizations Through Selective Match and Wakeup Range Limitation,IEEE Transactions on Very Large Scale Integration Systems,Vol. 14, No. 10, pp. 1089-1102, October 2006. (SCI, EI)
  10. C. -H. Chen and F.-F Lin,An Easy-to-Use Approach for Practical Bus-Based System Design,IEEE Transactions on Computers,Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI, EI)
  11. C. -H. Chen and A. K. Somani,Fault-Containment in Cache Memories for TMR Redundant Processor Systems,IEEE Transactions on Computers,Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI, EI)
  12. C. -H. Chen and A. K. Somani,Architecture Technique Trade-Offs Using Mean Memory Delay Time,IEEE Transactions on Computers,Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI, EI)
  13. Craig M. Wittenbrink, A. K. Somani, and C. -H. Chen,Cache Write Generate for Parallel Image Processing on Shared Memory Architectures,IEEE Transactions on Image Processing,Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI)
  14. C. -H. Chen and A. K. Somani,A Unified Architectural Tradeoff Methodology,ACM SIGARCH Computer Architecture News,Vol. 22, Iss. 2, pp. 348-357, April 1994.
  15. Chung-Ming Chen and Chung-Ho Chen,Window Architecture for Deblocking Filter in H.264/AVC,International Journal of Innovative Computing, Information and Control ,Vol. 3, No. 6, pp. 1677-1695, December 2007. (SCI, EI)
  16. Chung-Ho Chen, Chao-Hsien Hsu, and Chen-Chieh Wang,Scalable IPv6 Lookup/Update Design for High-Throughput Routers,Journal of Internet Technology,Vol. 8, No. 3, pp. 261-269, July 2007. (EI)
  17. Chung-Ming Chen and Chung-Ho Chen,An Efficient Pipeline Architecture for Deblocking Filter in H.264/AVC,IEICE Transactions on Information and Systems,Vol. E90-D, No.1 pp.99-107, January 2007. (SCI, EI)
  18. M.-D. Shieh, M.-H. Sheu, C.-H. Chen , and H.-F. LoA Systematic Approach for Parallel CRC Computations,Journal of Information Science and Engineering,Vol. 17, No. 3, pp. 445-461, May 2001. (SCI)
  19. C.-H. Chen and Akida Wu,Address Prediction Using a Bit-Matrix Indexing Scheme for Selective Update,Journal of Computers,Vol. 12 No.3, September 2000.
  20. C.-H. Chen and Akida Wu,Performance Evaluation of Load/Store Issue and Memory Access Policies,Journal of the Chinese Institute of Engineers,Vol.23, No. 6, pp. 697-709, 2000. (SCI, EI)
  21. C. -H. Chen,Exploring the Design Space of Cache Memories, Bus Width, and Burst Transfer Memory Systems,Journal of the Chinese Institute of Engineers,Vol.21, No. 3, pp.269-282, 1998. (SCI, EI)
  22. R. M. Haralick, A. K. Somani, C. Wittenbrink, R. Johnson, K. Cooper,L. G. Shapiro, I. T. Phillips, J. N. Hwang, W. Cheung, Y.H. Yao, C. H. Chen, L. Yang, B. Daugherty, B. Lorbeski, K. Loving, T. Miller, L. Parkins, et. al.Proteus: A Reconfigurable Computational Network for Computer Vision,Journal of Machine Vision and Applications,Vol. 8, No. 2, pp. 85-100, March 1995. (SCI, EI)
  23. P. D. Stigall and C. -H. Chen,A Performance Simulation of Local Area Networks Using CSMA/CD and Token Bus Protocols,Computers & Electrical Engineering,Vol. 16, No.3, 1990. (SCI, EI)
會議論文( Conference )
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  1. Chien-Hsuan Yen, Kuan-Chung Chen and Chung-Ho Chen, A memory-efficient NoC system for Op0enCL many-core platform, in the 2015 IEEE International Symposium on Circuits and Systems (ISCAS), May 24-27, 2015, Lisbon, Portugal.
  2. Ching-Wen Lin and Chung-Ho Chen, Unambiguous I-cache testing using software-based self-testing methodology, in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS), June 1-5, 2014 ,Melbourne VIC, Australian.
  3. Kuan-Chung Chen and Chung-Ho Chen, An OpenCL Runtime System for a Heterogeneous many-Core Virtual Platform , in the 2014 IEEE International Symposium on Circuits and Systems (ISCAS), June 1-5, 2014 ,Melbourne VIC, Australian.
  4. Jhe-Yu Liou and Chung-Ho Chen, Re-visit Blocking Texture Cache Design for Modern GPU, in the 11th International SoC Design Conference (ISOCC), Nov. 3-6, 2014, Jeju, Korea.
  5. Tzu-Hsuan Hsu, Ching-Wen Lin and Chung-Ho Chen, Using Condition Flag Prediction to Improve the Performance of Out-of-Order Processors, in the IEEE International Symposium on Circuits and Systems (ISCAS), May 19-23, 2013 ,Beijing, China.
  6. Chien-Te Liu, Kuan-Chung Chen and Chung-Ho Chen, CASL Hypervisor and its Virtualization Platform, in the IEEE International Symposium on Circuits and Systems (ISCAS), May 19-23, 2013 ,Beijing, China.
  7. Hsu-Yao Huang, Chi-Yuan Huang, and Chung-Ho Chen,Tile-Based GPU Optimizations through ESL Full System Simulation,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 20-23, 2012, Seoul, Korea.
  8. Chen-Chieh Wang, Sheng-Hsin Lo, Yao-Ning Liu, and Chung-Ho Chen,NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 20-23, 2012, Seoul, Korea.
  9. Chen-Chieh Wang and Chung-Ho Chen,An Optimized Cryptographic Processing Unit for IPsec Processors,in the 26th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC),June 19-22, 2011, Gyeongju, Korea.
  10. Kuan-Chung Chen and Chung-Ho Chen,A Synchronization Profiler for Hybrid Full System Simulation Platform,in the International SoC Design Conference (ISOCC-2010),Nov. 22-23, 2010, Incheon, Korea.
  11. Xie-Zeng Shen, Shin-Ying Lee, and Chung-Ho Chen,Full System Simulation with QEMU: an Approach to Multi-View 3D GPU Design,in the IEEE International Symposium on Circuits and Systems (ISCAS) ,May 30 - June 2, 2010, Paris, France.
  12. Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho Chen , and Kuen-Jong Lee,Full System Simulation and Verification Framework,in the Proceedings of the Fifth International Conference on Information Assurance and Security (IAS-2009) ,August 18-20, 2009, Xi'an, China.
  13. Chen-Chieh Wang, Ro-Pun Wong, Jing-Wun Lin, and Chung-Ho Chen,System-Level Development and Verification Framework for High-Performance System Accelerator,in the IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT) ,April 27-30, 2009, Hsinchu, Taiwan.
  14. Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee, Cheng-Wei Yen, Chung-Ho Chen,A Software-Based Test Methodology for Direct-Mapped Data Cache,in the IEEE Seventeenth Asian Test Symposium (ATS) ,November 24-27, 2008, Sapporo, Japan.
  15. Wei-Cheng Lin and Chung-Ho Chen,Avoiding Unnecessary Frame Memory Access and Multi-Frame Motion Estimation Computation in H.264/AVC,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 18-21, 2008, Seattle, Washington, USA.
  16. Tai-Hua Lu, Chung-Ho Chen , and Kuen-Jong Lee,A Hybrid Self-Testing methodology of Processor Cores,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 18-21, 2008, Seattle, Washington, USA.
  17. Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen ,Address Compression for Scalable Load/Store Queue Implementation,in the IEEE International Symposium on Circuits and Systems (ISCAS),May 18-21, 2008, Seattle, Washington, USA.
  18. Tai-Hua Lu, Chung-Ho Chen, and Kuen-Jong Lee,A Hybrid Software-Based Self-Testing methodology for Embedded Processor,in the ACM Symposium on Applied Computing (SAC),March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)
  19. Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho Chen,Power-efficient and Scalable Load/Store Queue Design via Address Compression,in the ACM Symposium on Applied Computing (SAC),March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)
  20. Wei-Cheng Lin and Chung-Ho Chen,A Data-Reuse Scheme for Avoiding Unnecessary Frame Buffer Accesses and Display RAM Accesses in MPEG-4 ASP Video Decoder,in the IEEE International SoC Conference (SOCC),September 26-29, 2007, Hsinchu, Taiwan.
  21. Yi-Cheng Chung, Stanley Lee, and Chung-Ho Chen,A Packet Forwarding Method for the iSCSI Virtualization Switch,in the 4th International Workshop on Storage Network Architecture and Parallel I/Os (SNAPI),September 24, 2007, San Diego, California, USA.
  22. Wei-Cheng Lin and Chung-Ho Chen,Reduction of Frame Memory Accesses and Motion Estimation Computations in MPEG-4 Video Encoder,in the 16th International Conference on Computer Communications and Networks (ICCCN),August 13-16, 2007, Honolulu, Hawaii, USA.
  23. Chung-Ho Chen, Yi-Cheng Chung, Chen-Hua Wang, and Han-Chiang Chen,Design of a Giga-bit Hardware Accelerator for the iSCSI Initiator,in the 31st Annual IEEE Conference on Local Computer Networks (LCN),November 14-16, 2006, Tampa, Florida, USA.
  24. Kuo-Su Hsiao and Chung-Ho Chen,Scheduler Optimization by Exploring Wakeup Locality,in the International Conference of Computer Engineering & Systems (ICCES),November 5-7, 2006, Egypt.
  25. Chung-Ming Chen, Chung-Ho Chen, Jian-Ping Zeng, and Chao-Tang Yu,Windows Processing for Deblocking Filter in H.264/AVC,in the Proceeding of the 32nd Annual Conference of the IEEE Industrial Electronics (IECON),November 7-10, 2006, Paris, France.
  26. Kuo-Su Hsiao and Chung-Ho Chen,Improving Scalability and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling,in the International Conference of Computer Design,October, 2006, USA. (EI)
  27. Wei-Cheng Lin and Chung-Ho Chen,Exploring Reusable Frame Buffer Data for MPEG-4 Video Decoding,in the IEEE International Symposium on Circuits and Systems (ISCAS),2006, Island of Kos, Greece. (EI)
  28. Chung-Ming Chen, Jian-Ping Zeng, Chung-Ho Chen, Chao-Tang Yu, and Yu-Pin Chang,Window Architecture for Deblocking Filter in H.264/AVC,in the 6th IEEE International Symposium on Signal Processing and Information Technology,August 27-30, 2006, Vancouver, Canada. (EI)
  29. Kuo-Su Hsiao and Chung-Ho Chen,An Efficient Wakeup Design for Energy Reduction in High-Performance Superscalar Processors,in the ACM SIGMicro International Conference on Computing Frontiers (CF) ,2005, Italy. (EI)
  30. Chung-Ming Chen and Chung-Ho Chen,A Memory Efficient Architecture for Deblocking Filter in H.264 Using Vertical Processing Order,in the IEEE International Conference on Intelligent Sensors, Sensor Networks, and Information Processing (ISSNIP),2005, Australia.
  31. Chung-Ming Chen and Chung-Ho Chen,Parallel Processing for Deblocking Filter in H.264/AVC,in the International Conference on Communications, Internet and Information Technology (CIIT),2005, Cambridge, USA. (EI)
  32. Chung-Ming Chen and Chung-Ho Chen,Alternative Processing Order with Efficient Architecture for Adaptive Deblocking Filter in H.264/AVC,in the International Conference on Communications, Internet, and Information Technology (CIIT),2005, Cambridge, USA. (EI)
  33. Chung-Ming Chen and Chung-Ho Chen,An Efficient Architecture for Deblocking Filter in H.264/AVC Video Coding,in the International Conference on Computer Graphics and Imaging (CGIM),2005, Honolulu, Hawaii, USA. (EI)
  34. Chung-Ming Chen and Chung-Ho Chen,An Efficient VLSI Architecture for Edge Filtering in H.264/AVC,in the International Conference on Circuits, Signals, and Systems,2005, Marina del Rey, CA, USA.
  35. F.-M Huang and C.-H. Chen,Memory Access Scheduling and Bank Precharge Strategies,in the poster proceeding of 12 th IEEE International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems,2004, Netherlands.
  36. Wei-Cheng Lin and Chung-Ho Chen,An Energy-Delay Efficient Power Management Scheme for Embedded System in Multimedia Applications,in Proceedings of The IEEE Asia Pacific Conference on Circuit & System (APCCAS),2004, Taiwan. (EI)
  37. N.-Y. Ker, and C.-H. Chen,An Effective SDRAM Power Mode Management Scheme for Performance and Energy Sensitive Embedded Systems,in the Proceeding of Asia and South Pacific Design Automation Conference (ASP-DAC) ,2003, Japan.
  38. M.-C. Chen, I.–J. Huang, and C.-H. Chen,Parameterized MAC Unit Implementation,in the Proceeding of Asia and South Pacific Design Automation Conference,2001, Japan.
  39. C.-H. Chen, M. -.H Sheu, M.-D. Shieh, T.-S, Li, and M.-T. Chen,Design and Implementation of a 10/100 Mbps Ethernet Switching Hub Controller,in the Proceeding of the IEEE Asia Pacific Conference on Communications,1998, Singapore.
  40. Ming-Hwa Sheu, Chung-Ho Chen, Ming-Der Shieh and Tzung-Shiue Li,A High Performance VLSI Architecture Design for 10M /100Mbps Ethernet Switching Fabric,in the Proceeding of International Conference on Consumer Electronics,1998, USA. (EI)
  41. C. -H. Chen and A. Wu,Microarchitecture Support for Improving the Performance of Load Target Prediction,in the Proceeding of 30 th Annual IEEE/ACM International Symposium on Microarchitecture,December 1-3, 1997, Research Triangle Park, NC, USA. (EI)
  42. C. -H. Chen and A. Wu,An Enhanced DLX-based Superscalar System Simulator,in the 3rd Annual Workshop on Computer Architecture Education,February, 1997, San Antonio, Texas, USA.
  43. C. -H. Chen and A. Wu,An Enhanced DLX-based Superscalar System Simulator,in the IEEE Computer Architecture Newsletter,pp.25-31, September, 1997.
  44. C. -H. Chen and A. K. Somani,A Unified Architectural Tradeoff Methodology,in the Proceeding of the 21st International Symposium on Computer Architecture,pp. 348-357, April 18-21, 1994, Chicago, USA. 國科會甲種研究獎 (EI)
  45. C. -H. Chen and A. K. Somani,A Cache Protocol for Error Detection and Recovery in Fault-Tolerant Computing Systems,in the 24 th International Symposium on Fault-Tolerant Computing,pp. 278-287, June 15-17, 1994, Austin Texas, USA. 國科會甲種研究獎 (EI)
  46. R. M. Haralick, Y-H, Yao, L. G. Shapiro, I. T. Phillips, A. K. Somani, J. N. Hwang, M. Harrington, C. Wittenbrink, C. -H. Chen, X. Liu, and S. Chen,Proteus: Control and Management System,in the Proceedings of Workshop on Computer Architectures for Machine Perception,pp. 101-108, December 15-17, 1993, New Orleans, USA.
  47. C. -H. Chen and A. K. Somani,Error Detection and Recovery in Fault-Tolerant Processor Systems Using Caches,in Proceeding of the ISMM International Conference on Parallel and Distributed Computing and Systems,pp. 388-393, 1992, Pittsburgh, PA, USA.
  48. C. -H. Chen and A. K. Somani,Fault-Tolerant Parallel Processing with Real-Time Error Detection and Recovery,in Proceeding of the 26th Asilomar Conference on Signals, Systems & Computers,pp. 994-998, 1992, USA.
  49. C. -H. Chen and A. K. Somani,Effects of Cache Traffics on Shared-Bus Multiprocessor Systems,in Proceedings of the International Conference on Parallel Processing,pp. I285-I288, 1992, USA. (EI)
  50. Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Hwang-J-N. Cheung-W. Yao-Y-H. Chen-C-H . Yang-L. Daugherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S.Proteus: a reconfigurable computational network for computer vision,Published by: IEEE Comput. Soc. Press. In Proceedings. 11th IAPR International Conference on Pattern Recognition.pp. 43-54, The Hague, Netherlands, 1992. (Judged among the 6 best papers).
  51. Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R. Cooper-K. Shapiro-L-G. Phillips-I-T. Jenq-Neng-Hwang. Cheung-W. Yung-Hsi-Yao. Chung-Ho-Chen . Yang-L. Duagherty-B. Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S.Proteus: a reconfigurable computational network for computer vision,in Proceedings of the SPIE - The International Society for Optical Engineering, vol.1659. pp. 54-76. 1992. Conf. Title: Image Processing and Interchange: Implementation and Systems, San Jose, CA, USA. SPIE. IS&T. 12-14 Feb. 1992. (EI)
  52. C. M. Wittenbrink, A. K. Somani, and C. -H. Chen,Cache Write Generate for High Performance Parallel Processing,Abstract presented in the 19 th International Symposium on Computer Architecture,1992, USA. (EI)
  53. A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G. Shapiro, J. N. Hwang, C. -H. Chen, R. Johnson, and K. Cooper,Proteus System Architecture and Organization,in the Proceeding of the Fifth International Parallel Processing Symposium,pp. 287-294, 1991.
  54. Yi-Ying Tsai, Ke-Jia Lee, and Chung-Ho Chen,Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems,in the Proceeding of the International Comput
  55. Po-Kai Chan, Chung-Ho Chen, and Cheng-Yeh Yu,An iWARP-Based TCP/IP Offload Engine,in the Proceeding of the 17th VLSI Design/CAD Symposium,August 8-11, 2006.
  56. W.-Z. Lin, and C.-H. Chen,10/100/1000 Mbps Ethernet MAC with Clock Management for AMBA System,in the Proceeding of the 13th VLSI Design/CAD Symposium,2002
  57. 盧偉聖、陳中和、蔡宜穎、林宇峰,特效光源之數位控制核心技術之研製,in the Proceeding of Taiwan Power Electronic Conference,2002
  58. C.-H. Chen, M.-D. Shieh, and Jimmy Shou,VLSI Architecture of an Instruction-Based Crypto Coprocessor,in the Proceeding of the 11th VLSI Design/CAD Symposium,2000
  59. 伍麗樵 , 黃胤傅 , 陳中和 , 陳惠淳 , 陳世仁 , 陳肇男 , 方志強 ,Download On Demand 多媒體影片租借系統之實作 ,第 15 屆全國技術及職業教育研討會論文集,pp. 171-179, 2000.
  60. S.-H. Sheu, C.-H. Chen, and T.-S Li,The Shared Bus Architecture Design and Chip Implementation for a 10M /100Mbps Ethernet Switching Fabric,in the Proceeding of the 8th VLSI
  61. J.-S. Lin, C.-H. Chen , C.-Y. Lin, and S.-H. Liu,The Application of Fuzzy Hopfield Neural Network for Vector Quantization in Image Compression,in the Proceeding of the fifth
  62. J.-W. Lin ,C.-H. Chen, A Processor Shield for Software-Based On-Line Self-Test, in IEEE Asia Pacific Conf. Circuits and Systems, October 25-28, 2016, Korea
  63. J.-W. Lin ,C.-H. Chen, Processor Shield for L1 Data Cache Software-Based On-line Self-testing, inAsia South Pacific Des. Autom. Conf. ,January 16-19, 2017, Japan
專利
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  1. 具多協定處理單位之儲存架構及方法 中華民國專利 I247991 號,, 2006.
  2. Multiprocessor system with write generate method for updating cache, United States patent, No. 5524212, June 1996.
  3. Storage structure and method utilizing multiple protocol processor units, United States patent, No. 7460550, Dec. 2008.
其他
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研究計劃
  1. 具易測試及除錯特性之智慧型低功率多核心系統之設計技術研發:從電子系統層級至矽晶片層級 ─, 子計畫(一):具自我測試特性之低功率處理器設計與其多核心全系統平台開發 Aug. 01, 2010 ~ Jul. 31, 2013 ( 3 years )
  2. 具能量效率之異質性架構系統中介語言GPU 之設計與實現-總計畫暨子計畫一:符合OpenCL/OpenGL ES Stack 的 HSAIL GPU 設計與實現MOST 104-2220-E-006-013
  3. 異質性運算平台之全系統技術開發與驗證MOST 103-2221-E-006 -266 -MY3
  4. 穿戴式顯示裝置於醫學之應用(1/3)MOST 104-3011-E-006-002
  5. 資通訊5G、SDN、低功率低電壓設計技術主題研究
  6. 測試機上通訊盒與雲端服務平台的通訊訊號品質與修正設計
  7. UPS web 網通系統
  8. 適用於 HSA 架構之 GPU 實現 (HSA-aware GPU Architecture Design with ESL)
開授課程
    指導學生
    本學年度 實驗室成員
    碩士班
    曾微中
    鄭基漢
    金育涵
    黃冠霖
    蘇郁翔
    紀旻志
    林柏榕
    吳庭嘉
    鄭博云
    陳惇介
    鄒宗翰
    廖松陽
    已畢業學生
    特殊榮譽
    1. 2009 年, 陳中和 教授指導學生 江定遠、黃煦堯 參加教育部九十七學年度全國大學校院積體電路設計競賽,榮獲 大學部標準元件數位電路設計組 優等 。
    2. 2007 年, 陳中和 教授指導學生 盧泰樺、蔡宜穎、林奕成、林璟汶 參加第七屆旺宏金矽獎半導體設計與應用大賽,全國各大學第一顆經由 Linux 驗證之 ARM ISA-like 管線化處理器 榮獲 優勝獎。
    3. 2006 年, 陳中和 教授指導學生實作功能齊全之 ARM9 相容處理器,Booting Linux 作業系統成功運轉,第一顆成大電機系、電通所、電資學院的全功能一般用途處理器。
    4. 2005 年, 陳中和 教授指導學生 詹博凱、余承燁 參加第三屆 Altera Nios 嵌入式處理器設計大賽,TCP/IP Offload Engine (TOE) for SOC System 榮獲 季軍。
    5. 2003 年, 陳中和 教授指導學生 許照賢、余承燁、陳漢威、熊恂緯 參加教育部九十一學年度大學院校矽智產 SIP設計競賽,榮獲 研究所 Soft IP 組 佳作 。台顧字第 0 九二 00 九八九九五號。
    6. 2000 年, 陳中和 教授指導學生參加教育部八十八學年度大學院校矽智產 SIP設計競賽,榮獲 研究所 FPGA 印證 特優獎 ,榮獲 研究所 Soft IP 組 優等獎 。台 ( 八九 ) 顧字第八九 0 九三九二三號。
    7. 1999 年, 陳中和 教授指導學生參加教育部八十七學年度大學院校矽智產 SIP設計競賽,榮獲 大學部 Soft IP 組 特優獎。台 ( 八八 ) 顧字第八八 0 九一七二六號。