NCKUEE Faculty Data
Chinese Version
Professor Meng-Hsueh Chiang
Address
ChiMei Building 4F R95402
Email
TEL
+886-6-2757575 ext.62418
Lab
System on Chip Laboratory Lab
(R95A06/ext.62400-2206)
Background
Educations
2001
Ph.D. in Electrical and Computer Engineering, University of Florida, Gainesville, Florida, USA
1995
M.S. in Electrical and Computer Engineering, University of Florida, Gainesville, Florida, USA
1992
B.S. in Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
Experiences
2017.8-2018.2
Visiting Scholar at University of California, Berkeley, CA, USA
2015-present
Professor at Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
2014-2015
Associate Professor at Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan
2003-2014
Faculty Member at National Ilan University, I-Lan, Taiwan
2012-2012
Visiting Scholar at University of California, Berkeley, CA, USA
2008
Visiting Scholar at Purdue University, West Lafayette, IN, USA
2001-2003
Senior Device Engineer, Technology Development Group, AMD, Sunnyvale, CA, USA
1995-2001
Graduate Research Assistant, SOI Group, University of Florida, Gainesville, FL, USA
1999-1999
Summer Intern, Strategic Technology Group, AMD, Sunnyvale, CA, USA
1996-1996
Hardware Engineer, Acer Inc., Taipei, Taiwan
Specialities
  • Semiconductor Device Physics
  • Semiconductor Devices Simulation
  • Compact Circuit Modeling for 6T-SRAM
  • Compact Device Modeling for FinFET, GAAFET and TFT
  • Compact Device Modeling for RRAM and the Application of Neural Network
Publication
Journal
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  1. Y.-T. Wu, F. Ding, M.-H. Chiang, J. F. Chen and T.-J. King Liu, "Simulation-Based Study of Low Minimum Operating Voltage SRAM With Inserted-Oxide FinFETs and Gate-All-Around Transisters," in IEEE Transactions on electron devices, vol 69, No.4, pp.1823-1829, Apr. 2022, doi:10.1109/TED.2022.3150645
  2. P.-A. Chen, W.-C. Hsu, M.-H. Chiang, "Bilayer Modulation With Dual Vacancy Filaments by Intentionally Oxidized Titanium Oxide for Multilayer-hBN RRAM," IEEE Transactions on Nanotechnology, volume: 20, Nov. 2021
  3. Y.-C. Huang, M.-H. Chiang, S.-J. Wang, J. G. Fossum, "TCAD-Based Assessment of the Lateral GAA Nanosheet Transistor for Future CMOS," IEEE Transactions on Electron Devices, Nov. 2021
  4. Y.-T. Wu, M.-H. Chiang, J. F. Chen, T.-J. K. Liu, "Simulation-Based Study of High-Permittivity Inserted-Oxide FinFET With Low-Permittivity Inner Spacers," IEEE Transactions on Electron Devices, vol. 68, pp. 5529 - 5534, Oct. 2021
  5. J.-W. Lee, and M.-H. Chiang, "Modeling of RRAM with Embedded Tunneling Barrier and Its Application in Logic in Memory," IEEE Journal of the Electron Devices Society, Jul. 2020
  6. X.-H. Wu, Ruijing Ge, P.-A. Chen, H. Chou, Z.-P. Zhang, Y.-F. Zhang, S. Banerjee, M.-H. Chiang, J. C. Lee, and D. Akinwande, "Thinnest nonvolatile memory based on monolayer h-BN," Advanced Materials, vol. 31, Apr. 2019
  7. Y.-T. Wu, F. Ding, D. Connelly, M.-H. Chiang, J. F. Chen, and T.-J. K. Liu, "Simulation-Based Study of High-Density SRAM Voltage Scaling Enabled by Inserted-Oxide FinFET Technology," IEEE Transactions on Electron Devices, vol. 66, pp. 1754 - 1759, Apr. 2019
  8. Y.-F. Hsieh, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D. D. Lu, and K.-H. Kao, "An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications," IEEE Transactions on Electron Devices (TED) vol. 65, pp. 855 - 859, Jan. 2018
  9. Y.-T. Wu, F. Ding, D. Connelly, P. Zheng, M.-H. Chiang, J. F. Chen, and T.-J. K. Liu, "Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology," IEEE Transactions on Electron Devices, Volume: 64, Issue: 10, Aug. 2017
  10. H.-Y. Liu, C.-W. Lin, W.-C. Hsu, C.-S. Lee, M.-H. Chiang,  W.-C. Sun,  S.-Y. Wei, and  S.-M. Yu, "Integration of Gate Recessing and In Situ Cl− Doped Al2O3 for Enhancement-Mode AlGaN/GaN MOSHEMTs Fabrication,"IEEE Electron Device Letters (EDL) Vol. 38, Jan. 2017
  11. Y.-T. Wu, F. Ding, D. Connelly, P. Zheng, M.-H. Chiang, J.-F. Chen and T.-J. King Liu, "Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology", IEEE Tran. Electron Devices, vol. 64, pp. 4193-4199, 2017
  12. P.-A. Chen, M.-H. Chiang and W.-C. Hsu, "All-zigzag graphene nanoribbons for planar interconnect application", Journal of Applied Physics 122, 034301, 2017
  13. Y.-C. Huang, S.-J. Wang and M.-H. Chiang, "S-shaped gate-all-around MOSFETs for high density design", EUROSOI 2017
  14. Y.-C. Huang, M.-H. Chiang, S.-J. Wang and J. G. Fossum, "GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node", EDS 2017
  15. C.-Y. Chen, J.-T. Lin and M.-H. Chiang, "Subthreshold Kink Effect Revisited and Optimized for Si Nanowire MOSFETs," TED 2016
  16. C.-Y. Chen, J. T. Lin and M.-H. Chiang, "Fabrication Variability in Multiple Gate MOSFETs: A Bulk FinFET Study," ECS 2016
  17. C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, "Subthreshold kink effect revisited and optimized for Si nanowire MOSFETs," IEEE Trans. Electron Devices, vol. 63, pp. 903-909, 2016.
  18. C.-Y. Chen, J. T. Lin, and M.-H. Chiang, "Fabrication variability in multiple gate MOSFETs: a bulk FinFET study," ECS Journal of Solid State Science and Technology, vol. 5, no. 4, pp. 3096-3100, 2016.
  19. M.-H. Chiang, K.-H. Hsu, W.-W. Ding, and B.-R. Yang, "A predictive compact model of bipolar RRAM cells for circuit simulations," IEEE Trans. Electron Devices, vol. 62, pp. 2176 - 2183, Jul. 2015.
  20. P. Zheng, Y.-B. Liao, N. Damrongplasit, M.-H. Chiang, and T.-J. King Liu, "Variation-aware comparative study of 10-nm GAA versus FinFET 6-T SRAM performance and yield," IEEE Trans. Electron Devices, vol. 61, pp. 3949-3954, Dec. 2014.
  21. Y.-B. Liao, M.-H. Chiang, N. Damrongplasit, W.-C. Hsu, and T.-J. King Liu, “Design of gate-all-around silicon MOSFETs for 6-T SRAM area efficiency and yield,” IEEE Trans. Electron Devices, vol. 61, pp. 2371-2377, Jul. 2014.
  22. Y.-B. Liao, M.-H. Chiang, Y.-S. Lai, and W.-C. Hsu, “Stack gate technique for dopingless bulk FinFETs,” IEEE Trans. Electron Devices, vol. 61, pp. 963-968, Apr. 2014.
  23. C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, “Investigation of discrete dopant induced variability in silicon nanowire MOSFETs using 3D simulation,” Internat. Journal of Nanotechnology, vol. 11, pp. 50-60, Mar. 2014.
  24. C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, “Performance optimization for the sub-22 nm fully depleted SOI nanowire transistors,” Solid-State Electronics, vol. 92, pp. 57-62, Feb. 2014.
  25. Y.-B. Liao, M.-H. Chiang, Y.-S. Lai, and W.-C. Hsu, “A pragmatic design methodology using proper isolation and doping for bulk FinFETs,” Solid-State Electronics, vol. 85, pp. 48-53, Jul. 2013.
  26. Y.-B. Liao, M.-H. Chiang, K. Kim, and W.-C. Hsu, “Assessment of structure variation in silicon nanowire FETs and impact on SRAM,” Microelectronics Journal,vol. 43, pp. 300-304, May 2012.
  27. K.-Y. Chu, S.-Y. Cheng, M.-H. Chiang, Y.-J. Liu, C.-C. Huang, T.-Y. Chen, C.-S. Hsu, W.-C. Liu, W.-Y. Cheng, and B.-C. Lin, “Comprehensive study of InGaP/InGaAs/GaAs dual channel pseudomorphic high electron mobility transistors,” Solid-State Electronics, vol. 72, pp. 22-28, Jun. 2012.
  28. K.-Y. Chu, S.-Y. Cheng, M.-H. Chiang, Y.-J. Liu, C.-C. Huang, T.-Y. Chen, C.-S. Hsu, W.-C. Liu, W.-Y. Cheng, and B.-C. Lin, “Effect of graded triple delta-doped sheets on the performance of GaAs based dual channel pseudomorphic high electron mobility transistors,” Superlattices and Microstructures, vol. 50, pp. 289-295, Oct. 2011.
  29. M.-H. Chiang, Y.-B. Liao, J.-T. Lin, W.-C. Hsu, Chu Yu, P.-C. Chiang, Y.-Y. Hsu, W.-H. Liu, S.-S. Sheu, K.-L. Su, M.-J. Kao,and M.-J. Tsai, “Low power design of phase-change memory based on a comprehensive model,” IET Computers & Digital Techniques, vol. 4, pp. 285-292, Jul. 2010.
  30. M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, “Optimal design of triple-gate devices for high-performance and low-power applications,” IEEE Trans. Electron Devices, vol. 55, pp. 2423 - 2428, Sep. 2008.
  31. D.-S. Chao, C. Lien, Y.-K. Chen, Y.-B. Liao, M.-H. Chiang, M.-J. Kao, and M.-J. Tsai, “A comprehensive parameterized model of phase-change memory cell for HSPICE circuit simulation,” Jpn. J. Appl. Phys., vol. 47, pp. 2696-2700, Apr. 2008.
  32. M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, “Random dopant fluctuation in limited-width FinFET technologies,” IEEE Trans. Electron Devices, vol. 54, pp. 2055-2060, Aug. 2007.
  33. M.-H. Chiang, K. Kim, C.-T. Chuang, and C. Tretz, “High-density reduced-stack logic circuit techniques using independent-gate controlled double-gate devices,” IEEE Trans. Electron Devices, vol. 53, pp. 2370-2377, Sep. 2006.
  34. S.-Y. Cheng, S.-I. Fu, K.-I. Chu, P.-H. Lai, L.-Y. Chen, W.-C. Liu, and M.-H. Chiang, “Improved dc and microwave performance of heterojunction bipolartransistors by full sulfur passivation,” J. Vac. Sci. Technol., vol. B22, pp. 669-674, no. 2, Mar/Apr 2006.
  35. M.-H. Chiang, C.-N. Lin, and G.-S. Lin, “Threshold voltage sensitivity to doping density in extremely scaled MOSFETs,” Semicond. Sci. Technol., vol. 21, pp. 190-193, Feb. 2006.
  36. M.-H. Chiang, K. Kim, C. Tretz, and C.-T. Chuang, “Novel high-density low-power logic circuit techniques using double-gate devices,” IEEE Trans. Electron Devices, vol. 52, pp. 2339-2342, Oct. 2005.
  37. S.-Y. Cheng, C.-Y. Chen, J.-Y. Chen, W.-C. Liu, W.-L. Chang, and M.-H. Chiang, “Comprehensive studies of InGaP/GaAs heterojunction bipolar transistors with different thickness of setback layers,” Superlattice and Microstructures, vol. 37, pp. 171-183, Mar. 2005.
  38. J. G. Fossum, L. Ge, M.-H. Chiang, V. P. Trivedi, M. M. Chowdhury, L. Mathew, G. O. Workman, and B-Y. Nguyen, "A process/physics-based compact model for nonclassical CMOS device and circuit design," Solid-State Electron., vol. 48, pp. 919-926, Jun. 2004.
  39. J. G. Fossum, L. Ge, and M.-H. Chiang, “Speed Superiority of Scaled Double-Gate CMOS,” IEEE Trans. Electron Devices, vol. 49, pp. 808-811, May 2002.
  40. J. G. Fossum, M.-H. Chiang, and T. W. Houston, “Design Issues and Insights for Low-Voltage High-Den sity SOI DRAM,” IEEE Trans. Electron Devices, vol. 45, pp. 1055-1062, May 1998.
Conference
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  1. Y.-C. Huang, M.-H. Chiang, S.-J. Wang, Y.-S. Lai, G.-L. Luo and K. Wu, "The Fabrication of Stacked Nanowire FETs with Multiple Isotropic Etching," 2021 Symposium on Nano-Device Circuits and Technologies, May. 2021
  2. Y.-H. Chen, C.-W. Tsai, T.-C. Chen, M.-H. Chiang, "TCAD-based sensitivity study of the channel stress and carrier mobility for the 3nm FinFET," INTERNATIONAL ELECTRON DEVICES & MATERIALS SYMPOSIUM 2021, Nov. 2021
  3. J.-L. Huang, Y.-C. Liu, M.-H. Chiang, "TCAD Based Study of the Impact of Traps on RF FinFETs," INTERNATIONAL ELECTRON DEVICES & MATERIALS SYMPOSIUM 2021, Nov. 2021
  4. J.-Y. Lin, Y.-G. Wang, C.-A. Wang, M.-H. Chiang, "Impact of Inner Spacer on Gate-Induced Drain Leakage Current in Nanosheet FET," INTERNATIONAL ELECTRON DEVICES & MATERIALS SYMPOSIUM 2021, Nov. 2021
  5. Y.-C. Huang, M.-H. Chiang, and S.-J. Wang, "The Process of Stacked Nanowire FETs with Repetitive Isotropic Etching," The 15th IEEE International Conference on Nano/Micro Engineered & Molecular Systems, Sep. 2020
  6. Y.-C. Huang, M.-H. Chiang, S.-J. Wang, Y.-S. Lai, G.-L. Luo, and K. Wu, "Process of Hybrid Fin/Planar Lateral MOSFET for High-Voltage Integrated Circuits," 2020 SNDT ,Apr. 2020
  7. J.-W. Lee, and M.-H. Chiang, "Compact Modeling of Selectorless Resistive Random Access Memory for Device Design Consideration," International Electron Devices & Materials Symposium, Oct. 2020
  8. P.-A. Chen, W.-C. Hsu, and M.-H. Chiang, "Gradual RESET modulation by intentionally oxidized titanium oxide for multilayer-hBN RRAM," 2019 IEEE 14th Nanotechnology Materials and Devices Conference (NMDC), Oct. 2020
  9. Y.-C. Huang, M.-H. Chiang, S.-J. Wang, Y.-S. Lai, G.-L. Luo and K. Wu, "Implementation of Hybrid Fin and Planar MOSFET for System-on-Chip Application," 2019 SNDT, Apr. 2019
  10. Y.-C. Huang, M.-H. Chiang, S.-J. Wang, "Speed Optimization of Vertically Stacked Gate-All-Around MOSFETs with Inner Spacers for Low Power and Ultra-Low Power Applications," 20th International Symposium on Quality Electronic Design (ISQED), Apr. 2019
  11. Y.-C. Huang, Yi-Ting Wu, J. F. Chen, S.-J. Wang, and M.-H. Chiang, "Hybrid FinFET Fabrication with Dummy Gate for Less Restrictive Alignment of Lateral Double Diffusion," INTERNATIONAL ELECTRON DEVICES & MATERIALS SYMPOSIUM 2019, Oct. 2019
  12. Y.-C. Huang, S. K. Gupta, M.-H. Chiang, and S.-J. Wang, "An Area Efficient Low-Voltage 6-T SRAM Cell Using Stacked Silicon Nanowires," International Conference on IC Design and Technolo, Jun. 2018
  13. J.-W. Lee, C.-H. Hsu, and M.-H. Chiang, "A Predictive Resistive RAM Compact Model with Synaptic Behavior for Circuit Simulations," Workshop of Compact Model, May. 2018
  14. S.-H. Chen, J.-W. Lee, M.-H. Chang, G.-L. Luo and K. Wu, "Cost-effective and Bulk Si-based Gate-all-around MOSFETs with Spacer-Etched Fabrication at 5nm Technology Node," Symposium on Nano Device Technology, Apr. 2018
  15. J.-Yi Chen, M.-Y. Chang, S.-H. Chen, J.-W. Lee, and M.-H. Chiang , "Body-Biasing Assisted Vmin Qptimization for 5nm-Node Multi-Vt FD-SOI," 2018 International Symposium on Quality Electronic Design, Mar. 2018
  16. R. Ge, X. Wu, M. Kim, P.-A. Chen, J. Shi, J. Choi, X. Li, Y. Zhang, M.-H. Chiang, Jack C. Lee and D. Akinwande, "Atomristors: Memory Effect in Atomically-thin Sheets and Record RF Switches," IEEE International Electron Devices Meeting, Dec. 2018
  17. Y.-C. Huang, S.-H. Chen, M.-H. Chiang and S.-J. Wang, "Design Considerations with Augmented Spacer Dielectric for Vertically Stacked Gate-All-Around MOSFET," IEEE Semiconductor Interface Specialists Conference, Dec. 2018
  18. S.-H. Chen, M.-Y. Chang, and M.-H. Chiang, "Performance Optimization of Gate-All-Around MOSFETs by Inner Spacers at 5-nm Technology Node," International Electron Devices & Materials Symposium, Nov. 2018
  19. P.-A. Chen, R.-J. Ge, J.-W. Lee, C.-H. Hsu, W.-C. Hsu, D. Akinwande, and M.-H. Chiang, "An RRAM with a 2D Material Embedded Double Switching Layer for Neuromorphic Computing," IEEE Nanotechnology Materials and Devices Conference, Oct. 2018
  20. M.-Y. Chang, L.-J. Wang, and M.-H. Chiang, "Insights to the Scaling Impact on Back-Gate Biasing for FD SOI MOSFETs," IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, Oct. 2018
  21. H.-Y. Liu, C.-S. Lee, C.-W. Lin, M.-H. Chiang, and W.-C. Hsu, "Gate structure engineering for enhancement-mode AlGaN/GaN MOSHEMT," 2017 75th Annual Device Research Conference (DRC), Jun. 2017
  22. Y.-C. Huang, M.-H. Chiang, S.-J. Wang, and J. G. Fossum, "GAAFET Versus Pragmatic FinFET at the 5nm Si-Based CMOS Technology Node," IEEE Journal of the Electron Devices Society (JEDS)[5,3], May. 2017
  23. J.-L. Lai, S.-H. Chen, M.-Y. Chang, M.-H. Chiang, W.-C. Hsu, G.-L. Luo and K. Wu, "Comprehensive Analysis of Interfacial Fin Isolation Oxide Charge for Bulk FinFETs", 48th IEEE Semiconductor Interface Specialists Conference 2017
  24. Y.-T. Wu, M.-H. Chiang, J.-F. Chen, F. Ding, D. Connelly and T.-J. King Liu, "High-density SRAM voltage scaling enabled by inserted-oxide FinFET technology", IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, pp. 1-3, 2017
  25. P. A. Chen, J. W. Lee, M. H. Chiang, and W. C. Hsu, "Simulation Based Study of Oxygen Plasma Induced Defects on Zigzag Graphene Nanoribbons", 232nd ECS Meeting 664, 2017
  26. J.-Y. Chen, S.-H. Chen, and M.-H. Chiang, "Three Operation Modes of 6T-SRAM Using 5nm-Node Multi-Vt FD-SOI MOSFETs", Nanotech 2017
  27. J.-L. Lai, M.-H. Chiang, W.-C. Hsu, G.-L. Luo and Kehuey Wu, "Subthreshold Characteristics of Bulk FinFETs with Fin Isolation Charge", SNDT 2017
  28. Y.-C. Huang, S.-J. Wang and M.-H. Chiang, "S-shaped Gate-All-Around MOSFETs for High Density Design", EuroSOI 2017
  29. M.-Y. Wu, J.-Y. Chen, and M.-H. Chiang,"Evaluation of 6T-SRAM with Multi-Gate Structures at 7 nm and 10 nm Technology Nodes", IEDMS 2016
  30. M.-Y. Wu and M.-H. Chiang,"Performance Evaluation of Stacked Gate-All-Around MOSFETs at 7 and 10 nm", Proc. 2016 International Symposium on Quality Electronic Design (ISQED) March 2016 Technology Nodes"
  31. J.-L. Lai, M.-H. Chiang, W.-C. Hsu, G.-Li Luo, and K. Wu, "Characterization of Oxide Interface Traps for Bulk FinFETs" Proc. 2016 Symp. Nano Device Technology, Hsinchu, Taiwan, May 2016
  32. Y.-C. Huang, M.-H. Chiang, and S.-J. Wang, "An Area Efficient Gate-All-Around Ring MOSFET", Proc. Silicon Nanoelectronics Workshop, Jun. 2016
  33. J.-H. Wang, J.-L. Lai, P.-A. Chen, M.-H. Chiang, W.-C. Hsu, W.-C. Sun, and S.-Y. Wei, “Al2O3 deposition by ultrasonic spray pyrolysis technique for non-planar MOS devices,” Proc. 46th IEEE Semiconductor Interface Specialists Conf., Arlington, Virginia, Dec. 2015, pp. 1-2.
  34. Y.-C. Huang, M.-H. Chiang, and S.-J. Wang, “Series resistance and channel doping impacts on 6-T SRAM with stacked nanowire MOSFETs,” Proc. 2015 Internat. Electron Devices and Materials Symp., Tainan, Taiwan, Nov. 2015, pp. 1-2.
  35. M.-Y. Wu, K. Wu and M.-H. Chiang, “Energy efficient FinFET design and optimization for the 10 nm node,” Proc. 2015 Symp. Nano Device Technology, Hsinchu, Taiwan, Sep. 2015, pp. 1-3.
  36. C.-Y. Chen, J. T. Lin, M.-H. Chiang, and W.-C. Hsu, “A steep subthreshold swing technique for gate-all-around SOI MOSFETs,” ECS Trans., vol. 66 (227th ECS Meeting, Chicago, Illinois), pp. 87-92, May 2015.
  37. Y.-C. Huang, M.-H. Chiang, W.-C. Hsu, and S.-Y. Cheng, “6-T SRAM performance assessment with stacked silicon nanowire MOSFETs,” Proc. 16th Internat. Symp. on Quality Electronic Design, Santa Clara, California, Mar. 2015, pp. 610-614.
  38. K.-C. Lin, W.-W. Ding, M.-H. Chiang, and S.-Y. Cheng, “A generic quadruple and cylindrical-gate MOSFET model via scale length,” Proc. 2014 Internat. Electron Devices and Materials Symp., Hualien, Taiwan, Nov. 2014, pp. 1-2.
  39. Y.-B. Liao and M.-H. Chiang, “Multi-threshold design methodology of stacked Si-Nanowire MOSFETs,” Proc. 2014 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conf., Millbrea, California, Oct. 2014, pp. 1-3.
  40. P. Zheng, Y.-B. Liao, N. Damrongplasit, M.-H. Chiang, W.-C. Hsu, and T.-J. King Liu, “Comparison of 10 nm GAA vs. FinFET 6-T SRAM performance and yield,” Proc. 2014 IEEE Silicon Nanoelectronics Workshop, Hololulu, Hawaii, Jun. 2014, pp. 1-2.
  41. Y.-B. Liao, M.-H. Chiang, and W.-C. Hsu, “Performance evaluation of stacked gate-all-around MOSFETs,” Proc. EuroSOI 2014, Tarragona, Spain, Jan. 2014, pp. 1-2.
  42. M.-H. Chiang, Y.-B. Liao, W.-W. Ding, and W.-C. Hsu, “High density and low power design of nanowire CMOS (invited),” Proc. 2013 Internat. Conf. SmallScience, Las Vegas, Nevada, Dec. 2013, pp. 138-139.
  43. K. Wu, W.-W. Ding, G.-L. Luo, and M.-H. Chiang, “10nm gate length FinFET design,” Proc. 2013 Internat. Electron Devices and Materials Symp., Nantou, Taiwan, Nov. 2013, pp.1 -2.
  44. Y.-B. Liao, M.-H. Chiang, and W.-C. Hsu, “Performance benchmarking for various bulk FinFETs,” Proc. 2013 Internat. Electron Devices and Materials Symp., Nantou, Taiwan, Nov. 2013, pp.1 -2.
  45. K. Wu, W.-W. Ding, and M.-H. Chiang, “Performance advantage and energy saving of triangular-shaped FinFETs,” Proc. Internat. Conf. on Simulation of Semiconductor Processes and Devices, Glasgow, Scotland, UK, Sep. 2013, pp.143-146.
  46. K.-H. Hsu, W.-W. Ding, and M.-H. Chiang, “A compact SPICE model for bipolar resistive switching memory,” Proc. 2013 IEEE International Conf. on Electron Devices and Solid-State Circuits, Hong Kong, Jun. 2013, pp.1-2.
  47. C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, “Quantum analysis of silicon nanowire gate capacitance,” Proc. 2013 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, Jun. 2013, pp. 1-6.
  48. Y.-B. Liao, M.-H. Chiang, and W.-C. Hsu, “Performance comparison of non-planar MOSFETs,” Nanotechnology 2013, vol. 2, pp. 9-12, Washington, DC, May2013.
  49. Y.-B. Liao, M.-H. Chiang, N. Damrongplasit, T.-J. King Liu, and W.-C. Hsu, “6-T SRAM cell design with gate-all-around silicon nanowire MOSFETs,” Proc. 2013 Internat. Symp. VLSI- Technology, Systems and Applications, Hsinchu, Taiwan, Apr. 2013,pp.-12
  50. C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, “Design insights of Si nanowire FETs: a simulation-based study,” Proc. 2012 Symp. Nano Device Technology, Hsinchu, Taiwan, Apr. 2012.
  51. C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, “Microscopic study of random dopant fluctuation in silicon nanowire transistors using 3D simulation,” Proc. 5th IEEE Internat. Nanoelectronics Conf., Singapore, Jan. 2013, pp. 267-270.
  52. M.-H. Chiang, Y.-B. Liao, W.-W. Ding, H. Li, and W.-C. Hsu, “Ultra-low power CMOS device design using nanometer-scale transistors (invited),” Proc. 2012 Internat. Conf. Small Science, Orlando, Florida, Dec. 2012, pp. 48-49.
  53. K.-H. Hsu, W.-W. Ding, M.-H. Chiang, Z.-H. Lin, S.-S. Sheu, H.-Y. Lee, Y.-S. Chen, and F. T. Chen, “Compact modeling of bipolar HfO2-based resistive switching memory,” Proc. 2012 Internat. Electron Devices and Materials Symp., Kaohsiung, Taiwan, Nov.2012,pp.1-2.
  54. C.-Y. Chen, J.-T. Lin, and M.-H. Chiang, “Impact of discrete random dopant on “undoped” silicon nanowire transistors,” Proc. 2012 Internat. Electron Devices and Materials Symp., Kaohsiung, Taiwan, Nov. 2012, pp.1 -2.
  55. M.-H. Chiang, “Modeling and analysis of Si nanowire MOSFETs (invited),” Proc. Symp. on Nano Device Technology, Hsinchu, Taiwan, Apr. 2012.
  56. Y.-B. Liao, M.-H. Chiang, W.-C. Hsu, Y.-S. Lai, and H. Li, “Comparative study of the gate structure in gate-all-around MOSFETs,” Proc. 2012 Symp. Nano Device Technology, Hsinchu, Taiwan, Apr. 2012.
  57. H. Li and M.-H. Chiang, “Design issues and insights of multi-fin bulk silicon FinFETs,” Proc. 2012 Internat. Symp. Quality Electronic Design, Santa Clara, California, Mar. 2012, pp. 723-726.
  58. Y.-B. Liao, M.-H. Chiang, K. Kim, and W.-C. Hsu, “A high-density SRAM design technique using silicon nanowire FETs,” Proc. 2011 Internat. Semiconductor Device Research Symp., College Park, Maryland, Dec. 2011, pp. 1-2.
  59. C.-Y. Chen, J.-T. Lin, M.-H. Chiang, Y.-C. Eng, and H. Li, “Capacitance modeling for silicon nanowire MOSFETs,” Proc. 2011 Internat. Electron Devices and Materials Symp., Taipei, Taiwan, Nov. 2011, pp. D1-4 1-2.
  60. Y.-B. Liao, M.-H. Chiang, W.-C. Hsu, C.-L. Lin, and H. Li, “Modeling technique for generic surrounding-gate CMOS,” Proc. 2011 Internat. Electron Devices and Materials Symp., Taipei, Taiwan, Nov. 2011, pp. D1-5 1-2.
  61. Y.-B. Liao, M.-H. Chiang, W.-C. Hsu, Y.-S. Lai, and H. Li, “Stack gate technique for feasible bulk FinFETs,” Proc. 2011 Solid State Devices and Materials,Nagoya, Japan, Sep. 2011.
  62. Y.-B. Liao, M.-H. Chiang, K. Kim, and W.-C. Hsu, “Variability study for silicon nanowire FETs,” Nanotechnology 2011, vol. 2, pp. 46-49, Boston,Massachusetts, Jun. 2011.
  63. Y.-B. Liao, W.-C. Hsu, M.-H. Chiang, H. Li, C.-L. Lin, and Y.-S. Lai, “Optimal device design of FinFETs on a bulk substrate,” Proc. 4th IEEE Internat. Nanoelectronics Conf., Tao-Yuan, Taiwan, Jun. 2011, pp.1-2.
  64. C.-L. Lin, M.-H. Chiang, Y.-B. Liao, H. Li, and W.-C. Hsu, “Implementation of a double-gate MOSFET compact model using Verilog-A,” Proc. 2011 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2011, pp. 13-18.
  65. Y.-B. Liao, M.-H. Chiang, W.-C. Hsu, and Y.-S. Lai, “Leakage suppression technique for bulk FinFETs,” Proc. Symposium on Nano Device Technology, Hsinchu, Taiwan, May 2011, ND-64, pp. 53.
  66. Y.-B. Liao, M.-H. Chiang, W.-C. Hsu, C.-L. Lin, and Y.-S. Lai, “Feasible design considerations of Bulk FinFETs,” Proc. 2010 Internat. Electron Devices and Materials Symp., Chungli, Taiwan, Nov. 2010, pp. B1-5 1-2.
  67. C. Y. Chen, J. T. Lin, and M. H. Chiang, “Scaling study of silicon nanowire FETs with junctionless structure,” Proc. 2010 Internat. Electron Devices and Materials Symp., Chungli, Taiwan, Nov. 2010, pp. D1-6 1-2.
  68. C.-Y. Chen, J.-T. Lin, M.-H. Chiang, and K. Kim, “High-performance ultra-low power junctionless nanowire FET on SOI substrate in subthreshold logic application,” Proc. 2010 IEEE Internat. SOI Conf., San Diego, California, Oct. 2010, pp. 1-2.
  69. C. Y. Chen, J. T. Lin, and M. H. Chiang, “A new design window of fully depleted Si nanowire FETs,” Proc. 2010 Solid State Devices and Materials, Tokyo, Japan, Sep. 2010, pp. 593-594.
  70. J. T. Lin, C. Y. Chen, and M. H. Chiang, “Pragmatic study of the nanowire FETs with nonideal gate structures,” Proc. 2010 IEEE Silicon Nanoelectronics Workshop, Hawaii, Jun. 2010, pp. 1.19 1-2.
  71. Y.-H. Chiu, Y.-B. Liao, M.-H. Chiang, C.-L. Lin, W.-C. Hsu, P.-C. Chiang, Y.-Y. Hsu, W.-H. Liu, S.-S. Sheu, K.-L. Su, M.-J. Kao, and M.-J. Tsai, “Impact of resistance drift on multilevel PCM design,” Proc. IEEE Interna. Conf. on IC Designand Technology, Grenoble, France, Jun. 2010, pp. 20-23.
  72. Y.-B. Liao, M.-H. Chiang, W.-C. Hsu, and Y.-S. Lai, “Assessment of a new MOS structure for Bio-MEMs sensor application,” Proc. Symposium on Nano Device Technology, Hsinchu, Taiwan, May 2010, pp. NB-04 1-3.
  73. J.-T. Lin, Y.-B. Liao, M.-H. Chiang, I.-H. Chiu, C.-L. Lin, W.-C. Hsu, P.-C. Chiang, S.-S. Sheu, Y.-Y. Hsu, W.-H. Liu, K.-L. Su, M.-J. Kao, and M.-J. Tsai, “Design optimization in write speed of multi-level cell application for phase change memory,” Proc. 2009 IEEE International Conf. on Electron Devices and Solid-State Circuits, Xian, China, Nov. 2009, pp. 525-528.
  74. M.-H. Chiang, C.-Y. Chen, and J.-T. Lin, “Advanced MOS device design considerations,” Proc. 2009 Internat. Electron Devices and Materials Symp., Taoyuan, Taiwan, Nov. 2009, pp. GC38 1-2.
  75. Y.-B. Liao, M.-H. Chiang, and W. –C. Hsu, “Impacts of buried oxide and substrate thickness on FinFETs,” Proc. 2009 Internat. Electron Devices and Materials Symp., Taoyuan, Taiwan, Nov. 2009, pp. A2-5 1-2.
  76. C.-Y. Chen, Y.-B. Liao, M.-H. Chiang, K. Kim, W.-C. Hsu, and S.-Y. Cheng, “Optimal design and performance assessment of extremely-scaled si nanowire FET on insulator,” Proc. 2009 IEEE Internat. SOI Conf., Foster City, California, Oct. 2009,pp.1-2
  77. C. Yu, C.-H. Sung, M.-H. Chiang, M.-H. Yen, and H.-T. Hu, “Low-error fixed-width modified booth multipliers,” Proc. The 20th VLSI Design/CAD Symposium, Hualien, Taiwan, Aug. 2009, pp. P1-11 1-4.
  78. A. Goel, S. Gupta, A. Bansal, M.-H. Chiang, and K. Roy, “Double-gate MOSFETs with asymmetric drain underlap: A device-circuit co-design and optimization perspective for SRAM,” Conf. Dig. The 67th Device Research Conference, University Park, Pennsylvania, Jun. 2009, pp. 57-58.
  79. Y.-B. Liao, C.-Y. Chen, M.-H. Chiang, and W.-C. Hsu, “Study of quantum mechanical effects in the multi-gate MOS devices,” Proc. 2009 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2009, pp. 55-56.
  80. C.-Y. Chen, Y.-B. Liao, M.-H. Chiang, S.-Y. Cheng, and W.-C. Hsu, “Impact of channel orientation on advanced MOS devices,” Proc. 2009 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2009, pp. 57-58.
  81. J.-T. Lin, Y.-B. Liao, M.-H. Chiang, and W.-C. Hsu, “Operation of multi-level phase change memory using various programming techniques,” Proc. IEEEInterna. Conf. on IC Design and Technology, Austin, Texas, May 2009, pp. 199-202.
  82. Y.-B. Liao, J.-T. Lin, M.-H. Chiang, and W.-C. Hsu, “Assessment of novel phase change memory programming techniques,” Proc. 2008 IEEE International Conf. on Electron Devices and Solid-State Circuits, Hong Kong, Dec. 2008, pp. 1-4.
  83. M.-H. Chiang, Y.-B. Liao, C.-Y. Chen, and W.-C. Hsu, “Performance evaluation of non-bulk MOSFETs: A simulation-based study (invited),” Proc. 2008 Internat. Electron Devices and Materials Symp., Taichung, Taiwan, Nov. 2008, pp. C.686 1-4.
  84. C.-Y. Chen, Y.-B. Liao, and M.-H. Chiang, “Impact of quantum mechanical effects on ultra-scaled nanowire transistors,” Proc. 2008 Internat. Electron Devices and Materials Symp., Taichung, Taiwan, Nov. 2008, pp. 110-112.
  85. C.-Y. Chen, Y.-B. Liao, and M.-H. Chiang, “Scaling study of nanowire and multi-gate MOSFETs,” Proc. The 9th International Conference on Solid-State and Integrated-Circuit Technology, Beijing, China, Oct. 2008, pp. 57-60.
  86. Y.-B. Liao, J.-T. Lin, and M.-H. Chiang, “Temperature-based phase change memory model for pulsing scheme assessment,” Proc. IEEE Interna. Conf. on IC Design and Technology, Grenoble, France, Jun. 2008, pp. 199-202.
  87. K.-C. Chan, C.-Y. Chen, and M.-H. Chiang, “Temperature dependence of impact ionization in nanoscale MOSFETs,” Proc. 2008 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2008, pp. 29-34.
  88. J.-N. Lin, K.-C. Chan, C.-Y. Chen, and M.-H. Chiang, “Discrete impurity dopant fluctuation in multi-fin FinFFTs: 3D simulation-based study,” Proc. 2007 IEEE Internat. Conf. on Electron Devices and Solid-State Circuits, Tainan, Taiwan, Dec. 2007, pp.57-7580
  89. Y.-B. Liao, Y.-K. Chen, and M.-H. Chiang, “An analytical compact PCM model accounting for partial crystallization,” Proc. 2007 IEEE Internat. Conf. on Electron Devices and Solid-State Circuits, Tainan, Taiwan, Dec. 2007, pp. 625-628.
  90. J.-N. Lin, K.-C. Chan, C.-Y. Chen, and M.-H. Chiang, “Analysis and modeling of short-channel effects for multi-gate MOSFETs,” Proc. 2007 Internat. Electron Devices and Materials Symp., Hsinchu, Taiwan, Nov. 2007, pp. PA-4 1-4.
  91. M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, “Asymmetrical triple-gate FET,” Proc. Internat. Conf. on Simulation of Semiconductor Processes and Devices, vol. 12, Vienna, Austria, Sep. 2007, pp. 389-392.
  92. Y.-B. Liao, Y.-K. Chen, and M.-H. Chiang, “Phase change memory modeling using Verilog-A,” Proc. 2007 IEEE Internat. Behavioral Modeling and Simulation Conf., San Jose, California, Sep. 2007, pp. 159-162.
  93. D. S. Chao, Y. K. Chen, Y. B. Liao, M. H. Chiang, C. Lien, M. J. Kao, and M. J. Tsai, “Comprehensive HSPICE model of phase change memory cell for static and transient programming,” Proc. 2007 Internat. Conf. on Solid State Devices and Materials, Ibaraki,Japan, Sep. 2007, pp. 830-831.
  94. J.-N. Lin and M.-H. Chiang, “Dopant fluctuation effects in double-gate MOSFETs: the 2D and 3D comparison,” Proc. 2007 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2007, pp. 13-14.
  95. Y.-B. Liao, Y.-K. Chen, and M.-H. Chiang, “Implementation of compact memory model using Verilog-A,” Proc. 2007 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2007, pp. 9-10.
  96. J.-N. Lin and M.-H. Chiang, “Impact of discrete impurity atoms on the double-gate MOSFET scaling,” Proc. 2006 Internat. Electron Devices and Materials Symp., Tainan, Taiwan, Dec. 2006, pp. 403-405.
  97. T.-N. Lin, M.-H. Chiang, and J.-N. Lin, “Analysis of corner effects in triple-gate devices,” Proc. 2006 Internat. Electron Devices and Materials Symp., Tainan, Taiwan, Dec. 2006, pp. 421-423.
  98. M.-H. Chiang, T.-N. Lin, K. Kim, C.-T. Chuang, and C. Tretz, “Optimal design of nanoscale triple-gate devices,” Proc. 2006 IEEE Internat. SOI Conf., Niagara Falls, New York, Oct. 2006, pp. 143-144.
  99. M.-H. Chiang, J.-N. Lin, K. Kim, and C.-T. Chuang, “Discrete dopant fluctuation in limited-width FinFET for VLSI circuit application: a theoretical study,”Proc. 2006 IEEE Interna. Conf. on IC Design and Technology, Padova, Italy, May 2006,pp.88-91
  100. J.-N. Lin and M.-H. Chiang, “Macromodeling of dopant fluctuation impact on extremely scaled MOSFETs,” Proc. 2006 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2006, pp. 60-61.
  101. J.-N. Lin and M.-H. Chiang, “Dopant discretization effects in nanoscale MOSFETs,” Proc. 2005 Electron Devices and Materials Symp., Kaohsiung, Taiwan, Nov. 2005, pp. 29.
  102. T.-N. Lin and M.-H. Chiang, “On the short-channel effects of multiple-gate MOSFETs,” Proc. 2005 Electron Devices and Materials Symp., Kaohsiung, Taiwan, Nov. 2005, pp. 45.
  103. M.-H. Chiang, K. Kim, C.-T. Chuang, and C. Tretz , “Single polysilicon gate high-density logic using independently-controlled double-gate devices,” Proc. 2005 IEEE Asian Solid-State Circuits Conf., Hsinchu, Taiwan, Nov. 2005, pp. 353-356.
  104. M.-H. Chiang, K. Kim, C.-T. Chuang, and C. Tretz, “High-density logic techniques with reduced-stack double-gate MOSFETs,” Proc. 2005 IEEE Internat. SOI Conf., Honolulu, Hawaii, Oct. 2005, pp. 85-86.
  105. M.-H. Chiang, “Double-gate CMOS modeling techniques,” Proc. the Twelfth Military Symposium on Fundamental Science, Kaohsiung, Taiwan, Jun. 2005, pp.c18-c22.
  106. C.-N. Lin, C.-L. Chen, C.-H. Pu, L.-L. Lai, C.-M. Lo, and M.-H. Chiang, “Threshold voltage dependence on channel doping for decananometer MOSFETs,”Proc. 2005 Conf. on Microelectronics Technology and Applications, Kaohsiung, Taiwan, May 2005,pp.2-627
  107. M.-H. Chiang, K. Kim, C. Tretz, and C.-T. Chuang, “Novel high-density low-power high-performance double-gate logic techniques,” Proc. 2004 IEEE Internat. SOI Conf., Charleston, South Carolina, Oct. 2004, pp. 122-123.
  108. M.-H. Chiang, J. X. An, Z. Krivokapic, and B. Yu, “Double-Gate CMOS evaluation for 45nm node technology,” Tech. Proc. 2003 Nanotechnology Conf., San Francisco, California, vol. 2, Feb. 2003, pp. 326-329.
  109. J. G. Fossum, L. Ge, and M.-H. Chiang, “A physics-based compact model for nano-scale DG and FD/SOI MOSFETs,” Tech. Proc. 2003 Nanotechnology Conf.,San Francisco, California, vol. 2, Feb. 2003, pp. 274-277.
  110. S. Shankar, M.-H. Chiang, and M. M. Pelella, “Impact of gate tunneling on the nature of charge dump current in 100nm PD SOI technology,” Proc. 2002 IEEE Internat. SOI Conf., Williamsburg Virginia, Oct. 2002, pp. 41-42.
  111. M.-H. Chiang and J. G. Fossum, “A process-based compact model for double-gate MOSFETs,” Proc. 2001 Internat. Symp. on SOI Technology and Devices,Washington, DC, ECS vol. 2001-3, Mar. 2001, pp. 421-426.
  112. M. M. Pelella, J. G. Fossum, M.-H. Chiang, G. O. Workman and C. Tretz, “Analysis and Control of Hys teresis in PD/SOI CMOS,” Tech. Digest 1999 IEEE Internat. Electron Devices Meeting, pp. 831-834, Dec. 1999.
Patent
more
less
  1. High-density logic techniques with reduced-stack multi-gate field effect transistors, U.S. Patent 7,382,162, with C.-T. K. Chuang and K. Kim, Jun. 2008.
  2. Body-Tied-to-Body SOI CMOS Inverter Circuit,?U.S.?Patent 6,498,371, with S. Krishnan and J. G. Fossum, Dec. 2002.
Others
more
less
  1. PI, FinFET and Stacked Nanowire SRAM Design and Tool Development, (8/2017-1/2018)
  2. PI, Design technique and modeling of low power synaptic electronics using resistive memory, (8/2017-7/2018)
  3. Pi, Development of IGZO TFT AC and DC models using Verilog-A, (8/2017-10/2017)
  4. PI, Feasibility study of lateral and vertical array of gate-all-around MOSFETs, (8/2016-7/2017)
  5. PI, Design methodology of UTBOX SOI FinFETs and stacked GAA nanowire transistors, Ministry of Science and Technology of Taiwan (New Partnership Program for the Connection to the Top Labs in the World), 9/2015-8/2017
  6. PI, Development of stacked silicon nanowire MOSFETs, Ministry of Science and Technology of Taiwan, 8/2014-7/2015
  7. PI, Modeling and analysis of RRAM, National Science Council of Taiwan, 8/2013-7/2014
  8. Co-PI, Pragmatic study for silicon nanowire-based SRAM, National Science Council of Taiwan (New Partnership Program for the Connection to the Top Labs in the World), 11/2011-10/2012
  9. PI, Impact of process variation on junctionless nanowire transistors: simulation-based study, National Science Council of Taiwan, 8/2011-7/2013
  10. PI, Compact modeling of non-bulk Si transistors for VLSI application, National Science Council of Taiwan (International Industrial), 9/2010-12/2010
  11. PI, Compact nanowire transistor modeling for circuit simulation, National Science Council of Taiwan, 8/2009-7/2011
  12. PI, Performance evaluation of high performance CMOS VLSI using nanowire FETs, National Science Council of Taiwan (International Industrial), 8/2009-9/2009
  13. PI, Investigation of nanowire transistor scaling, National Science Council of Taiwan, 8/2008-7/2009
  14. PI, Impact of discrete dopant on nanoscale high performance CMOS VLSI, National Science Council of Taiwan (Research Abroad Program), 6/2008-9/2008
  15. PI, Investigation of three-dimensional discrete dopant distribution in nanoscale MOSFETs, National Science Council of Taiwan, 8/2007-7/2008
  16. PI, Analysis and modeling on the short-channel effects of multiple-gate MOSFETs, National Science Council of Taiwan, 8/2006-7/2007
  17. PI, Performance assessment of nanometer-scale multiple-gate MOSFETs under different gate control schemes, National Science Council of Taiwan, 8/2005-8/2006
  18. PI, The impact of gate structure on the characteristics of nanometer-scale multiple-gate MOSFETs, National Science Council of Taiwan, 8/2004-7/2005
  19. PI, Threshold voltage sensitivity to doping fluctuation for nano-scale MOSFETs, National Science Council of Taiwan, 12/2003-7/2004
Projects
  1. PI, FinFET and Stacked Nanowire SRAM Design and Tool Development, (8/2017-1/2018)
  2. PI, Design technique and modeling of low power synaptic electronics using resistive memory, (8/2017-7/2018)
  3. Pi, Development of IGZO TFT AC and DC models using Verilog-A, (8/2017-10/2017)
  4. PI, Feasibility study of lateral and vertical array of gate-all-around MOSFETs, (8/2016-7/2017)
  5. PI, Design methodology of UTBOX SOI FinFETs and stacked GAA nanowire transistors, Ministry of Science and Technology of Taiwan (New Partnership Program for the Connection to the Top Labs in the World), 9/2015-8/2017
  6. PI, Development of stacked silicon nanowire MOSFETs, Ministry of Science and Technology of Taiwan, 8/2014-7/2015
  7. PI, Modeling and analysis of RRAM, National Science Council of Taiwan, 8/2013-7/2014
  8. Co-PI, Pragmatic study for silicon nanowire-based SRAM, National Science Council of Taiwan (New Partnership Program for the Connection to the Top Labs in the World), 11/2011-10/2012
  9. PI, Impact of process variation on junctionless nanowire transistors: simulation-based study, National Science Council of Taiwan, 8/2011-7/2013
  10. PI, Compact modeling of non-bulk Si transistors for VLSI application, National Science Council of Taiwan (International Industrial), 9/2010-12/2010
  11. PI, Compact nanowire transistor modeling for circuit simulation, National Science Council of Taiwan, 8/2009-7/2011
  12. PI, Performance evaluation of high performance CMOS VLSI using nanowire FETs, National Science Council of Taiwan (International Industrial), 8/2009-9/2009
  13. PI, Investigation of nanowire transistor scaling, National Science Council of Taiwan, 8/2008-7/2009
  14. PI, Impact of discrete dopant on nanoscale high performance CMOS VLSI, National Science Council of Taiwan (Research Abroad Program), 6/2008-9/2008
  15. PI, Investigation of three-dimensional discrete dopant distribution in nanoscale MOSFETs, National Science Council of Taiwan, 8/2007-7/2008
  16. PI, Analysis and modeling on the short-channel effects of multiple-gate MOSFETs, National Science Council of Taiwan, 8/2006-7/2007
  17. PI, Performance assessment of nanometer-scale multiple-gate MOSFETs under different gate control schemes, National Science Council of Taiwan, 8/2005-8/2006
  18. PI, The impact of gate structure on the characteristics of nanometer-scale multiple-gate MOSFETs, National Science Council of Taiwan, 8/2004-7/2005
  19. PI, Threshold voltage sensitivity to doping fluctuation for nano-scale MOSFETs, National Science Council of Taiwan, 12/2003-7/2004
Classes
111 Academic year2
111 Academic year1
110 Academic year 2
110 Academic year 1
109 Academic year 2
109 Academic year 1
108 Academic year 2
107 Academic year 1
106 Academic year 2
105 Academic year 2
105 Academic year 1
104 Academic year 2
104 Academic year 1
Students
Current Academic Year Lab Members
Ph.D.
Jia-Wei Lee
Ming-Yu Zhang
Xin-Yu Ji
Zi-Fei Chen
Jia-An Wang
Master
Kai-Yu Liang
Nian-Ting You
Wei-Chieh Chang
Yu-Chuan Lin
Han-Wei Wang
Yi-Feng Hung
Yu-Jia Liu
Yu-Chen Dai
Yong-Han Lai
Ting-Zheng Chen
Bo-Cheng Yan
Xiang-Ching Huang
Graduates of all Previous Years
Ph.D.
103
Yi-Bo Liao
110
Yi-Ting Wu
111
Ya-Chi Huang   Bo-Ann Chen
Master
104
Jia-Heng Wang
105
Meng-Yen Wu
106
Ru-Liang Lai   Hsin-Yu Chi   Cheng-Yi Chen
107
Bo-Ren Yang   Shi-Hao Chen    Shin-Han Li
108
Bo-Lun Chiou   Li-Jing Wang   Wen-Jia Liang
109
Chun-Hsiang Hsu   Yu-Sen Xu    Bo-Yu Zhao
110
Zhao-lin Huang   Yu-Xuan Chen   Jia-Ying Lin
111
Yu-Gan Wang    Jun-Wei Tsai    Yu-Che Liu   Tzu-Cheng Chen
112
De-Xiang Jair   Po-Chih Chen   Chun-Yi Yeh   Jia-Wei Chen   Yun-Zhung Zheng   Tzu-Chin Chou
Honors
  1. Best Paper Award at the Internat. Electron Devices and Materials Symp. (2013, 2015)
  2. Distinguished Teaching Award, Yilan City Education Association (2012)
  3. National Science Council Young Faculty Grant (2011)
  4. Program for Promoting Teaching Excellence Award, National Ilan University (2011)
  5. Who's Who in the World, 2007, 2009. (Marquis Who's Who)
  6. Second runner-up in Signal Processing and Communications Group, National Microcontroller Application System Contest (2004, 2009)
  7. Best Poster Paper Award at the Internat. Electron Devices and Materials Symp. (2006)
NCKU EE