NCKUEE Faculty Data
Chinese Version
Professor Ming-Der Shieh
Address
ChiMei Building 5F R95509
Email
TEL
+886-6-2757575 ext.62364
Lab Weblink
VLSI Design Lab
(R95514/ext.62400-2885)
Background
Educations
1993
Ph.D., Electrical Engineering, Michigan State University, U.S.A.
1986
M.S., Electronic Engineering, National Chiao Tung University, Taiwan
1984
B.S., Electrical Engineering, National Cheng Kung University, Taiwan
Experiences
2009/08-present
Professor, Department of Electrical Engineering, National Cheng Kung University
2017/05-present
Adjunct Research Fellow, Office of Science and Technology, Executive Yuan
2016/08-present
Chairman, Taiwan IC Design Society
2016/01-present
HiMax Chair Professor  
2014/02-present
Senior Research Consultant, Information and Communications Research Laboratories, Industrial Technology Research Institute
2014/08-2017/07
Chairman,Department of Electrical Engineering, National Cheng Kung University
2014/08-2016/07
Vice Chair, Taiwan IC Design Society
2010/02-2014/01
Deputy General Director, Information and Communications Research Laboratories, Industrial Technology Research Institute
2012/05-2014/01
Director, Semiconductor Industry Promotion Office, Industrial Development Bureau, Ministry of Economic Affairs
2010/02-2014/01
Vice Chair, Taiwan Semiconductor Industry Association, IC Design Committee
2010/08-2012/07
Vice Chair, Taiwan IC Design Society
2002/08-2009/07
Associate Professor, Department of Electrical Engineering, National Cheng Kung University
2005/01-2009/12
Consultant, National Chip Implementation Center
1999/08-2002/07
Chairman, Department of Electronic Engineering, National Yunlin University of Science & Technology
1993/08-2002/07
Associate Professor, Department of Electronic Engineering, National Yunlin University of Science & Technology
2002/01-2002/12
Consultant, Electron Technology Information Magazine,
1999/07-2000/06, 2001/02-2001/12
Consultant, Industrial Technology Research Institute,
1988/06-1989/08
Engineer, R&D Division, United Microelectronic Corporation,
Specialities
  • VLSI Design and Test
  • VLSI Architecture for Digital Signal Processing
  • Digital Communication
  • Computer-Aided Design
Publication
Journal
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  1. J.S. Lin, Y.T. Hwang, S.H. Fang, and M.D. Shieh, 2015, October, “Low-complexity High-throughput QR Decomposition Design for MIMO Systems,” IEEE Transactions on VLSI Systems, vol. 23, no. 10, pp. 2342-2346.
  2. H.F. Luo, Y.J. Liu, and M.D. Shieh, 2015, October, “Efficient Memory Addressing Algorithms for FFT Processor Design,” IEEE Transactions on VLSI Systems, vol. 23, no. 10, pp. 2162-2172.
  3. D.W. Yang, L.C. Chu, C.W. Chen, J. Wang, and M.D. Shieh, 2015, June, “Depth-reliability-based Stereo Matching Algorithm and its VLSI Architecture Design,” IEEE Transactions on Circuit and System for Video Technology, vol. 25, no. 6, pp. 1038-1050.
  4. W.C. Lin, J.H. Ye and M.D. Shieh, 2014, February, “Scalable Montgomery Modular Multiplication Architecture with Low Latency and Low Memory Bandwidth Requirement," IEEE Transactions on Computers, vol. 63, no. 2, pp 475-483.
  5. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2013, December, “Subspace-Based Blind Channel Estimation by Separating Real and Imaginary Symbols for Cyclic-Prefixed Single-Carrier Systems,” IEEE Transactions on Broadcasting, vol. 59, no. 4, pp 698-704.
  6. Y.F. Chou, D. M. Kwai, M.D. Shieh and C.W. Wu, 2013, September, “Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs,” IEEE Transactions on Circuits and Systems I, vol. 60, no. 9, pp 2343-2351.
  7. C.C Lo, C.W. Hsu and M.D. Shieh, 2013, April, “Low-complexity multi-standard variable length coding decoder using tree-based partition and classification,” IET Image Processing, vol. 7, Iss. 3, pp 185-190.
  8. Y.K. Lu and M.D. Shieh, 2013, January, “Initial settings of Berlekamp-Massey algorithm for efficient hardware implementation,” Electronics Letters, vol. 49, no. 3, pp. 190-191.
  9. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2012, November, “Blind Channel Estimation for Cyclic Prefix-free Orthogonal Frequency-division Multiplexing Systems with Particular Input Symbols,” IET Communications, vol. 6, Iss. 16, pp. 2654-2660.
  10. S.F. Lei, C.C. Lo, C.C. Kuo and M.D. Shieh, 2012, June, “Low-power context-based adaptive binary arithmetic encoder using an embedded cache,” IET Image Processing, vol. 6, Iss. 4, pp. 309-317.
  11. M.D. Shieh, S.H. Fang, S.C. Tang and D.W. Yang, 2012, February, “Low-complexity Memory Access Architectures for Quasi-cyclic LDPC Decoders,” IEICE Transactions on Information and Systems, vol. E95.D, no. 2, pp. 549-557.
  12. M.D. Shieh and Y.K. Lu, 2011, August, "Design and Implementation of a Low-Complexity Reed-Solomon Decoder for Optical Communication Systems," IEICE Transactions on Information and Systems, vol. E94.D, no. 8, pp. 1557-1564.
  13. C.L. Wey, S.Y. Lin, P.Y. Tsai and M.D. Shieh, 2011, July, “Reconfigurable Homogenous Multi-Core FFT Processor Architectures for Hybrid SISO/MIMO OFDM Wireless Communications,” IEICE Transactions on Fundamentals of Electronics Communications and Computer Sciences, vol. E94A, no. 7, pp 1530-1539.
  14. W.C. Lin, M.D. Shieh and C.M. Wu, 2011, May, "Design of High-Speed Iterative Dividers in GF(2m)," Journal of Information Science and Engineering, vol. 27, no. 3, pp. 953-967.
  15. S.Y. Lin, C.L. Wey and M.D. Shieh, 2010, November, “Low-cost FFT processor for DVB-T2 applications,” IEEE Transactions on Consumer Electronics, vol. 56, no. 4, pp 2072-2079.
  16. C.C. Lo, S.T. Tsai and M.D. Shieh, 2010, August, "Reconfigurable Architecture for Entropy Decoding and Inverse Transform in H.264," IEEE Transactions on Consumer Electronics, vol. 56, no. 3, pp. 1670-1676.
  17. M.D. Shieh and W.C. Lin, 2010, August, "Word-Based Montgomery Modular Multiplication Algorithm for Low-Latency Scalable Architectures," IEEE Transactions on Computers, vol. 59, no. 8, pp. 1145-1151.
  18. J.H. Chen, M.D. Shieh and W.C. Lin, 2010, August, "A High-Performance Unified-Field Reconfigurable Cryptographic Processor," IEEE Transactions on VLSI Systems, vol. 18, no. 8. pp.1145-1158.
  19. Y.K. Lu and M.D. Shieh, 2010, July, “High-Speed Low-Complexity Architecture for Reed-Solomon Decoders,” IEICE Transactions on Information and Systems, vol. E93.D, no. 7, pp. 1824-1831.
  20. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2010, January, “Blind Channel Estimation for SIMO-OFDM Systems without Cyclic Prefix,” IEICE Transaction on Fundamentals, vol. E93.A, no. 1, pp. 339-343.
  21. M.D. Shieh, Y.K. Lu and S. M. Chung, 2009, December, “Efficient Reed-Solomon Decoder Design for Multi-Mode Applications,” Journal of Electrical Engineering, vol.16, no.6, pp.503-516.
  22. M.D. Shieh, J.H. Chen, W.C. Lin and H.H. Wu, 2009, September, “A New Algorithm for High-Speed Modular Multiplication Design,” IEEE Transaction on Circuits and Systems I, vol.55, no.11, pp.3430-3437.
  23. M.D. Shieh, J.H. Chen, W.C. Lin and C.M. Wu, 2009, September, “An Efficient Multiplier/Divider Design for Elliptic Curve Cryptosystem over GF(2m),” Journal of Information Science and Engineering, vol.25, no.5, pp.1555-1573.
  24. M.D. Shieh, T.P. Wang and D.W. Yang, 2009, April, “Low-Power Register-Exchange Survivor Memory Architectures for Viterbi Decoders,” IET Circuits, Devices & Systems , vol. 3, no. 2, pp. 83-90.
  25. C.C. Lo, Y.J. Zeng and M.D. Shieh, 2009, April, “Design of A High-Throughput CABAC Encoder,” IEICE Transaction on Information and Systems, vol. E92.D, no. 4, pp. 681-688.
  26. C.L. Wey, M.D. Shieh and S.Y. Lin, 2008, December, “Algorithms of Finding the First Two Minimum Values and Their Hardware Implementation,” IEEE Transactions on Circuits and Systems I, vol.55, no.11, pp.3430-3437.
  27. M.D. Shieh, T.P. Wang and C.M. Wu, 2008, September, “Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders,” IEICE Transactions on Information and Systems , vol. E91-D, no. 9, pp. 2300-2311.
  28. M.D. Shieh, J.H. Chen, H.H. Wu and W.C. Lin, 2008, September, “A New Modular Exponentiation Architecture for Efficient Design of RSA Cryptosystem,” IEEE Transactions on VLSI Systems, vol. 16, pp. 1151-1161.
  29. M.D. Shieh, J.H. Chen and C.M. Wu, 2006, February, “High-Speed Design of Montgomery Inverse Algorithm over GF(2m),” IEICE Transactions on Fundamentals, vol. E89-A, no. 2, pp. 559-565.
  30. C.M. Wu, M.D. Shieh, C.H. Wu, Y.T. Hwang and J.H. Chen, 2005, April, “VLSI Architectural Design Tradeoffs for Sliding-Window Log-MAP Decoders,” IEEE Transactions on VLSI Systems, vol. 13, no. 4, pp. 439-447.
  31. C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2004, March, “High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2m),” IEEE Transactions on Computers, vol. 53, no. 3, pp. 375-380.
  32. C.M. Wu, M.D. Shieh, M.H. Hu and M.C. Lee, 2003, November, “Design and Implementation of Punctured Viterbi Decoder with Full Decoding Capability for DAB System,” Journal of Chinese Institute of Electrical Engineering, vol. 10, no. 4, pp. 331-343.
  33. C.M. Wu, M.D. Shieh and C.H. Wu, 2003, November, “Exploring General Memory Structures in Turbo Decoders Using Sliding Window MAP Algorithm,” IEICE Transactions on Communications, vol. E86-B, no. 11, pp. 3163-3173.
  34. M.D. Shieh, C.M. Wu, Y.T. Hwang, H.F. Lo and M.H. Hu, 2003, August “Realization of Area-Efficient FFT Processors,” Journal of Chinese Institute of Electrical Engineering, vol. 10, no. 3, pp. 269-280.
  35. C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2002, May, “Novel Algorithms and VLSI Design for Division over GF(2m),” IEICE Transactions on Fundamentals, vol. E85-A, no. 5, pp. 1129-1139.
  36. C.H. Wu, M.D. Shieh, J.Y. Huang, H.W. Chang and C.M. Wu, 2002, March, “Comparative Study of Iterative Turbo Decoding Algorithms,” Journal of Science and Technology, vol. 11, no. 2, pp.91-99.
  37. M.D. Shieh, M.H. Sheu, C.H. Chen and H.F. Lo, 2001, May, “A Systematic Approach for Parallel CRC Computations,” Journal of Information Science and Engineering, pp. 445-461.
  38. M.D. Shieh, C.M. Wu, H.H. Chou, M.H. Chen and C.L. Liu, 1999, August, “Design and Implementation of a DAB Channel Decoder,” IEEE Transactions on Consumer Electronics, vol. 45, no. 3, pp. 553-562.
  39. M.D. Shieh, H.H. Chou and C.M. Wu, 1999, May, “Design and Implementation of Deinterleaver and L3 Interface for DAB System,” CCL Technical Journal (電腦與通訊月刊), vol. 79, pp. 38-44.
  40. M.D. Shieh, C.M. Wu, and H.H., Chou, 1999, May, “Design of the Variable-rate Punctured Viterbi Decoder for DAB System,” CCL Technical Journal (電腦與通訊月刊), vol. 79, pp. 30-37.
  41. C.L. Wey and M.D. Shieh, 1998, September, “Design of a High-Speed Square Generator,” IEEE Transactions on Computers, vol. 47, no. 9, pp. 1021-1026.
  42. M.D. Shieh, C.L. Wey, and P.D. Fisher, 1993, November, “Fault Effects in Asynchronous Sequential Logic Circuits,” IEE Proceedings-E Computers and Digital Techniques, vol.140, pp.327-332.
Conference
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  1. H.J. Hsu and M.D. Shieh, “VLSI Architecture of Polynomial Multiplication for BGV Homomorphic Encryption,” International Symp. Circuits and Systems, May 2020.
  2. H.C. Hsiao, C.W. Chen ,J. Wang, M.D. Shieh, P.Y. Chen, 2019, April, "Architecture-aware Memory Access Scheduling for High-throughput Cascaded Classifiers," accepted, 2019 IEEE 22nd International Symposium on Design and Diagnostics of Electronic Circuits & Systems
  3. J.N. Ji and M.D. Shieh, 2019, May, "Efficient Comparison and Swap on Fully Homomorphic Encrypted Data," accepted, 2019 IEEE International Symposium on Circuits and Systems
  4. J.H. Ye, S.Q. Chen and M.D. Shieh, 2018, May, “Minimizing ESOP Expressions for Fully Homomorphic Encryption,” accepted, 2018 IEEE International Symposium on Circuits and Systems.
  5. C.W. Chen, W.Y. Hsiao, T.Y. Lin, J. Wang and M.D. Shieh, 2018, May, “Fast Keyframe Selection and Switching for ICP-based Camera Pose Estimation,” accepted, 2018 IEEE International Symposium on Circuits and Systems.
  6. J.H. Ye and M.D. Shieh, 2018, April, “High-Performance NTT Architecture for Large Integer Multiplication,” accepted, 2018 IEEE International Symposium on VLSI Design, Automation & Test.
  7. C.W. Chen, M.D. Shieh, J.M. Lu, H.L. Huang and Y.H. Chen, 2017, September, “Content-aware Line-based Power Modeling Methodology for Image Signal Processor,” 2017 IEEE SOC Conference (SOCC), pp. 346-350.
  8. C.W. Chen, F.K. Hsu, D.W. Yang, J. Wang and M.D. Shieh, 2016, October, “Effective Model Construction for Enhanced Prediction in Example-based Super-Resolution,” 2016 IEEE Asia Pacific Conference on Circuits and Systems, pp. 156-159.
  9. W.J. Chen, C.W. Chen, J. Wang and M.D. Shieh, 2016, September, “Effective registration for multiple users AR system ,” 2016 IEEE International Symposium on Mixed and Augmented Reality (ISMAR), pp. 270-271.
  10. T.Y. Lin, C.W. Chen, J. Wang and M.D. Shieh, 2016, September, “Motion-aware iterative closest point estimation for fast visual odometry,” 2016 IEEE International Symposium on Mixed and Augmented Reality (ISMAR), pp. 268-269.
  11. C.W. Chen, F.K. Hsu, D.W. Yang, J. Wang and M.D. Shieh, 2016, May, “Fast Model Searching and Combining for Example Learning-based Super-Resolution,” 2016 IEEE International Symposium on Circuits and Systems, pp. 1994-1997.
  12. D.W. Yang, Y.C. Chang, C.W. Chen, J. Wang and M.D. Shieh, 2015, October, “Low-Complexity Depth Generation Using Vanishing Cues for General Applications,” 2015 International Conference on Innovation, Communication and Engineering, pp. 1-4.
  13. H.F. Luo, M.D. Shieh and K.H. Lee, 2015, June, “A radix-2/3/22/23 MDC architecture for variable-length FFT processors,” 2015 IEEE International Conference on Consumer Electronics - Taiwan, pp. 180-181.
  14. H.F. Luo and M.D. Shieh, 2015, June, “Efficient memory management scheme for pipelined shared-memory FFT processors,” 2015 IEEE International Conference on Consumer Electronics - Taiwan, pp. 178-179.
  15. C.W. Chen, C.H. Su, D.W. Yang, J. Wang, C.C. Lo and M.D. Shieh, 2015, May, “High-Quality Texture Compression Using Adaptive Color Grouping and Selection Algorithm,” 2015 IEEE International Symposium on Circuits and Systems, pp. 2760-2763.
  16. J.S. Lin, M.D. Shieh, C.Y. Liu and D.W. Yang, 2015, April, “Efficient Highly-Parallel Turbo Decoder for 3GPP LTE-Advanced,” 2015 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
  17. J.H. Ye, S.H. Huang and M.D. Shieh, 2014, June, “An Efficient Countermeasure against Power Attacks for ECC over GF(p),” 2014 IEEE International Symposium on Circuits and Systems, pp. 814-817.
  18. Y.K. Lu, S.M. Chung and M.D. Shieh, 2014, April, “Low-complexity Architecture for Chase Soft-decision Reed-Solomon Decoding,” 2014 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
  19. D.W. Yang, L.C. Chu, C.W. Chen, J.M. Gan, J. Wang and M.D. Shieh, 2014 April, “Low Complexity Stereo Matching Algorithm Using Adaptive Sized Square Window,” 2014 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
  20. J.H. Ye, T.W. Hung and M.D. Shieh, 2013, April, “Energy-efficient Architecture for Word-based Montgomery Modular Multiplication Algorithm,” 2013 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
  21. D.W. Yang, C.W. Chen, C.H. Chang, Y.C. Chang, M.D. Shieh, J. Wang and C.C. Lo, 2012, December, “Face detection architecture design using hybrid skin color detection and cascade of classifiers,” 2012 Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 543-546.
  22. S.H. Fang, J.Y. Chen, J.S. Lin, M.D. Shieh, W.C. Huang and J.Y. Hsu, 2012, December, “Blind channel estimation for MIMO-OFDM systems with repeated time-domain symbols,” 2012 Asia Pacific Conference on Circuits and Systems (APCCAS), pp. 37-40.
  23. D.W. Yang, J.S. Lin, S.H. Fang, C.F. Lin and M.D. Shieh, 2012, December, “High Performance Turbo-MIMO System Design with Iterative Soft-detection and Decoding,” 2012 Asia-Pacific Signal and Information Processing Association Annual Submit and Conference (APSIPA-ASC), pp. 1-4.
  24. J.S. Lin, Y.T. Hwang, P.H. Chu, M.D. Shieh and S.H. Fang, 2012, May, “An Efficient QR Decomposition Design for MIMO Systems,” 2012 IEEE International Symposium on Circuits and Systems, pp. 1508-1511.
  25. S.H. Wang, W.C. Lin, J.H. Ye and M.D. Shieh, 2012, May, “Fast Scalable Radix-4 Montgomery Modular Multiplier,” 2012 IEEE International Symposium Circuits and Systems, pp. 3049-3052.
  26. W.C. Lin, J.H. Ye, D.W. Yang, S.Y. Huang, M.D. Shieh and J. Wang, 2012, May, “Efficient Scissoring Scheme for Scanline-based Rendering of 2D Vector Graphics,” 2012 IEEE International Symposium Circuits and Systems, pp. 766-769.
  27. Y.K. Lu and M.D. Shieh, 2012, April, “Efficient Architecture for Reed-Solomon Decoder,” 2012 IEEE International Symposium on VLSI Design, Automation & Test, pp. 1-4.
  28. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2012, November, “Subspace-based Blind Channel Estimation with Periodicity for OFDM Systems without Cyclic Prefix,” in Proc. 2011 IEEE Region 10 Conference (TENCON), pp. 470-473.
  29. M.D. Shieh, S.H. Fang, S.C. Tang and D.W. Yang, 2012, September, “VLSI Design of Area-efficient Memory Access Architectures for Quasi-cyclic LDPC Codes,” in Proc. 2011 IEEE SOC Conference (SOCC), pp. 242-246.
  30. D.W. Yang, M.D. Shieh, W.H. Kuo and J.Wang, 2010, December, "Efficient Protocol Converter Generation for System Integration," 2010 Asia Pacific Conference on Circuits and Systems, pp. 903-906.
  31. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2010, December, "A Signal Permutation Method for Cyclic-Prefix-Free OFDM Channel Estimation," 2010 Asia Pacific Conference on Circuits and Systems, pp. 656-659.
  32. Y.K. Lu and M.D. Shieh, 2010, November, "Design of High-Throughput Re-Encoder for Soft-Decision Reed-Solomon Decoding," 2010 International Symposium on Next-Generation Electronics (ISNE), pp. 36-39.
  33. J. S. Lin, S.H. Fang, M.D. Shieh and Y.H. Jen, 2010, November, "Design of High-Throughput MIMO Detectors Using Sort-Free and Early-Pruned Techniques," TENCON 2010 IEEE Region 10 Conference, pp. 1513-1516.
  34. C. C. Lo, C.W. Hsu and M.D. Shieh, 2010, October. "Area-Efficient H.264 VLC Decoder Using Sub-tree Classification," The Sixth International Conference on Intelligent Information Hiding and Multimedia Signal Processing, pp. 284-287.
  35. H. F. Lo, M.D. Shieh, Y.J. Liu and C.M. Wu, 2010, May, “Efficient Memory Management for FFT Processors” 2010 IEEE International Symposium on Circuits and Systems, pp. 3737-3740.
  36. W. C. Lin, M.D. Shieh and C.M. Wu, 2010, May, “Design of High-Speed Bit-Serial Divider in GF(2m)” 2010 IEEE International Symposium on Circuits and Systems, pp. 713-716.
  37. Y. K. Lu, M.D. Shieh and C.M. Wu, 2010, May, “Low-Complexity Reed-Solomon Decoder for Optical Communications,” 2010 IEEE International Symposium on Circuits and Systems, pp. 4173-4176.
  38. S. H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2010, May, “Subspace-Based Blind Channel Estimation for OFDM Systems with Conjugate-Symmetric Property,” in Proc. 2010 IEEE Vehicular Technology Conference, pp. 1-5.
  39. Y. K. Lu and M.D. Shieh, 2010, April, “Low-complexity Reed-Solomon Decoder for Blu-ray Disc Applications,” 2010 IEEE International Symposium on VLSI Design, Automation & Test, pp. 359-362.
  40. J. J. Zhu, W.C. Lin, J.H. Ye and M.D. Shieh, 2009, November, “Efficient Software-based Self-test Methods for Embedded Digital Signal Processors,” The 18 th Asian Test Symposium, pp. 206-211.
  41. C. C. Lo, J.G. Luo and M.D. Shieh, 2009, August, “Hardware/Software Co-design of Resource Constrained Real-Time Systems,” Fifth International Conference on Information Assurance and Security, vol. 1, pp. 177-180.
  42. Y. L. Tsai, C.C. Lo, J.G. Luo and M.D. Shieh, 2009, May, “Efficient Inverse Transform design for Multi-Standard Video Coding Applications,” 2009 International Symposium on Digital Life Technologies.
  43. W. C. Lin, M.D. Shieh and C.M. Wu, 2009, May “Flexible GF(2m) Divider Design for Cryptographic Applications,” 2009 IEEE International Symposium on Circuits and Systems, pp. 25-28.
  44. S. H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2009, May, “A Generalized Blind Channel Estimation Algorithm for OFDM Systems with Cyclic Prefix,” 2009 IEEE International Symposium on Circuits and Systems, pp. 2469-2472.
  45. C. C. Lo, S.T. Tsai and M.D. Shieh, 2009, April, “A Reconfigurable Architecture for Entropy Decoder and IDCT in H.264,” 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp. 279-282.
  46. Y.K. Lu, M.D. Shieh and W.H. Kuo, 2009, April, “Design of High-Speed Errors-and-Erasures Reed-Solomon Decoders for Multi-Mode Applications,” 2009 IEEE International Symposium on VLSI Design, Automation & Test, pp. 199-202.
  47. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2009, April “Modified Subspace-Based Channel Estimation Algorithm for OFDM Systems,” 2009 IEEE Vehicular Technology Conference, pp. 1-5.
  48. W.C. Tasi, M.D. Shieh, W.C. Lin and C.L. Wey, 2008, November, “Design of Square Generator with Small Look-up Table,” in Proc. 2008 IEEE Asia-Pacific Conference on Circuits and Systems.
  49. W.C. Lin, J.H. Chen and M.D. Shieh, 2008, May, “A New look-up table-based multiplier/squarer design for cryptosystems over GF(2m),” 2008 IEEE International Symposium on Circuits and Systems, pp. 464-467.
  50. J.H. Chen, W.C. Lin, H.S. Wu and M.D. Shieh, 2008, May, “High-Speed Modular Multiplication Design for Public-key Cryptosystems," 2008 IEEE International Symposium on Circuits and Systems, pp. 680-683.
  51. J.H. Chen, S.J. Huang, W.C. Lin, Y.K. Lu and M.D. Shieh, 2008, July, “Exploration of Low-Cost Configurable S-Box Designs for AES Applications,” in Proc. The Fifth International Conference on Embedded Software and Systems, pp. 422-428.
  52. C.C. Lo, Y.J. Zeng and M.D. Shieh, 2007, October, “Design and Test of A High-Throughput CABAC Encoder,” TENCON 2007 IEEE Region 10 Conference.
  53. W.C. Lin, M.D. Shieh, J.H. Chen, C.M. Wu and H.S. Wu, 2007, October, “A Combined Multiplication/Division Algorithm for Cost-Effective Design of Elliptic Curve Cryptosystem over GF(2m),” TENCON 2007 IEEE Region 10 Conference.
  54. J.H. Chen, H.S. Wu, M.D. Shieh and W.C. Lin, 2007, May, “A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA Cryptosystem,” 2007 IEEE International Symposium on Circuits and Systems, pp. 3780-3783.
  55. J.H. Chen, M.D. Shieh, H.S. Wu and W.C. Lin, 2006, December, “Asynchronous Design of Modular Multiplication Using Adaptive Radix Computation,” 2006 IEEE Asia-Pacific Conference on Circuits and Systems, pp. 607-610.
  56. M.D. Shieh, Y.K. Lu, S.M. Chung and J.H. Chen, 2006, May, “Design and Implementation of Efficient Reed-Solomon Decoders for Multi-Mode Applications,” 2006 IEEE International Symposium on Circuits and Systems, pp. 289-292.
  57. M.D. Shieh, T.P. Wang, C.M. Wu and C.M. Huang, 2006 May, “Efficient Path Metric Access for Reducing Interconnect Overhead in Viterbi Decoders,” 2006 IEEE International Symposium on Circuits and Systems, pp. 4815-4818.
  58. J.S. Lin, C.K. Lee, M.D. Shieh and J.H. Chen, 2006 May, “High-Speed CRC Design for 10 Gbps Applications,” 2006 IEEE International Symposium on Circuits and Systems, pp. 3177-3180.
  59. J.H. Chen, M.D. Shieh and C.M. Wu, 2005, May, “Concurrent Algorithm for High-Speed Point Multiplication in Elliptic Curve Cryptography,” 2005 IEEE International Symposium on Circuits and Systems, pp. 5254-5257.
  60. T.P. Wang, C.Y. Tsai, M.D. Shieh, and K.J. Lee, 2005, April, “Efficient Test Scheduling for Hierarchical Core Based Design,” IEEE VLSI-TSA International Symposium on VLSI Design, Automation & Test, pp. 200-205.
  61. J.H. Chen, M.D. Shieh, and C.M. Wu, 2004, December, “High-Speed VLSI Design for Montgomery Inverse over GF(2m),” 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp. 25-28.
  62. M.D. Shieh, S.C. Shen, Y.C. Lin and K.J. Lee, 2004, December, “Efficient Testing and Design-for-Testability Schemes for Multimedia Cores: A Case Study on DCT Circuits,” 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp. 177-180.
  63. C.M. Wu, M.D. Shieh, C.H. Wu, Y.T. Hwang, J.H. Chen and H.F. Lo, 2004, May, “VLSI Architecture Exploration for Sliding-Window Log-MAP Decoders,” 2004 IEEE International Symposium on Circuits and Systems, pp. 513-516.
  64. C.M. Wu, M.D. Shieh, H.F. Lo and M.H. Hu, 2003, May, “Implementation of Channel Demodulator for DAB Systems,” 2003 IEEE International Symposium on Circuits and Systems, vol. 2, pp.25-28.
  65. C.M. Wu, M.D. Shieh and C.H. Wu, 2002, August, “Memory Arrangements in Turbo Decoders Using Sliding-Window MAP Algorithm,” 2002 IEEE International Symposium on Circuits and Systems, pp. V-557-560.
  66. C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2002, August, “An Area-Efficient Systolic Division Circuit over GF(2m) for Secure Communication,” 2002 IEEE International Symposium on Circuits and Systems, pp. V-733-736.
  67. C.M. Wu, M.D. Shieh, C.H. Wu and M.H. Sheu, 2001, May, “VLSI Architecture of Extended In-Place Path Metric Update for Viterbi Decoders,” 2001 IEEE International Symposium on Circuits and Systems, pp. 206-209.
  68. H.F. Lo, M.D. Shieh and C.M. Wu, 2001, May, “Design of an Efficient FFT Processor for DAB System,” 2001 IEEE International Symposium on Circuits and Systems, pp. 654-657.
  69. C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2001, May, “Systolic VLSI Realization of a Novel Iterative Division Algorithm over GF(2m): a High-Speed, Low-Complexity Design,” 2001 IEEE International Symposium on Circuits and Systems, pp. 33-36.
  70. M.D. Shieh, H.F. Lo and M.H. Sheu, 2000, December “High-Speed Generation of LFSR Signatures,” The 9th Asian Test Symposium, pp.222-227.
  71. M.D. Shieh, C.H. Wu, M.H. Sheu, J.L. Sheu and C.H. Wu, 2000, August, “Asynchronous Implementation of Modular Exponentiation for RSA Cryptography,” The Second IEEE Asia Pacific Conference on ASICs, pp. 191-194.
  72. C. H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2000, August, “Novel Iterative Division Algorithm over GF(2m) and Its Semi-Systolic VLSI Realization,” IEEE Midwest Symposium on Circuits and Systems, pp. 280-283.
  73. C.M. Wu, M.D. Shieh, C.H. Wu and M.H. Sheu, 2000, May, “An Efficient Approach for In-Place Scheduling of Path Metric Update in Viterbi Decoder,” 2000 IEEE International Symposium on Circuits and Systems, pp. III-61~III-64.
  74. M.H. Sheu, S.C. Tsai and M.D. Shieh, 1999, August, “A New Algorithm and VLSI Architecture Design for Lossless Coding of VQ Codevector Index,” The First IEEE Asia Pacific Conference on ASICs.
  75. M.D. Shieh, C.M. Wu, H.H. Chou, M.H. Chen and C.L. Liu, 1999, June, “Design and Implementation of a DAB Channel Decoder,” 1999 IEEE International Conference on Consumer Electronics, pp. 74-75.
  76. M.D. Shieh, C.H. Wu, M.H. Sheu, C.H. Wu and J.L. Sheu, 1999, June, “A VLSI Architecture of Fast High-Radix Modular Multiplication for RSA Cryptosystem,” 1999 IEEE International Symposium on Circuits and Systems, pp. I-500-I-503.
  77. J.C. Huang, C.M. Wu, M.D. Shieh and C.H. Wu, 1999, June, “An Area-Efficient Versatile Reed-Solomon Decoder for ADSL,” 1999 IEEE International Symposium on Circuits and Systems, pp. I-517-I-520.
  78. M.H. Sheu, C.H. Chen, M.D. Shieh and T.S. Li, 1998, June, “A High Performance VLSI Architecture Design for 10/100M bps Ethernet Switching Fabric,” 1998 IEEE International Conference on Consumer Electronics, pp. 26-27.
  79. C.H. Chen, M.H. Sheu, M.D. Shieh, T.S. Li and M.T. Chen, ”Design and Implementation of 10/100 Mbps Ethernet Switching Hub Controller,” IEEE Asia Pacific Conference on Communications, 1998.
  80. J.L. Sheu, M.D. Shieh, C.H. Wu and M.H. Sheu, 1998, June, “A Pipelined Architecture of Fast Modular Multiplication for RSA Cryptography,” 1998 IEEE International Symposium on Circuits and Systems, pp. II-121-II-124.
  81. M.D. Shieh, M.H. Sheu, C.M. Wu and W.S. Ju, 1998, June, “Efficient Management of In-Place Path Metric Update and its Implementation for Viterbi Decoder,” 1998 IEEE International Symposium on Circuits and Systems, pp. IV-449-IV-452.
  82. M.H. Sheu, M.D. Shieh and S.W. Liu, 1998, June, “A VLSI Architecture Design with Lower Hardware Cost and Less Memory for Separable 2-D Wavelet Transform,” 1998 IEEE International Symposium on Circuits and Systems, pp. V-457-V-460.
  83. C.H. Wu, M.D. Shieh, M.R. Wang and J.S. Wang, 1997, October, “A Versatile Multimedia Codec System Based on the TMS320C80 Digital Signal Processor,” 1997 Workshop on Consumer Electronics: Digital Video and Multimedia, pp. B4-2/6-B4-2/11.
  84. W.S. Ju, M.D. Shieh and M.H. Sheu, 1997, August, “A Low-Power VLSI Architecture for the Viterbi Decoder,” 1997 Midwest Symposium on Circuits and Systems, pp.1201~1204.
  85. M.D. Shieh, M.H. Sheu and Y.C. Hsu, 1997, August, “A High-Performance VLSI Architecture for MAPS Criterion Motion Estimation,” 1997 Midwest Symposium on Circuits and Systems, pp. 1221~1224.
  86. M.H. Sheu, M.D. Shieh and S.W. Liu, 1997, August, “A Low-Cost VLSI Architecture Design for Non-separable 2-D Discrete Wavelet Transform,” 1997 Midwest Symposium on Circuits and Systems, pp. 1217~1220.
  87. M.H. Sheu, M.D. Shieh, S.W. Liu and C. Dou, 1997, August, “An Efficient Hardware Design Approach from System-Level Specification,” 1997 Midwest Symposium on Circuits and Systems, pp. 1213~1216.
  88. M.R. Wang, J.S. Wang, Y.T. Huang, M.H. Sheu and M.D. Shieh, 1997, September, “A Versatile Signal Processing Board for Real-Time Multimedia Communication,” 7th International Symposium on IC Technology, Systems & Applications, pp. 331-334.
  89. Y.S. Ke, M.D. Shieh and M.H. Sheu, 1997, September, “On the Implementation of Wave-Pipelined Multipliers in Lookup Table-Based FPGAs,” 7th International Symposium on IC Technology, Systems & Applications, pp. 434-437.
  90. M.D. Shieh, M.H. Sheu, H.R. Wang and H.C. Cheng, 1997, September, “Dichotomy-Based Constrained Encoding for Low Switching Activity in Asynchronous Finite State Machines,” 7th International Symposium on IC Technology, Systems & Applications, pp. 509-512.
  91. C. Dou, M.H. Sheu and M.D. Shieh, 1997, “Performance Evaluation for HW/SW Codesign of Communication Protocols,” 1997 Asia-Pacific Conference on Hardware Description Language.
  92. C. Dou and M.D. Shieh, 1996, October, “A CAM-Based VLSI Architecture for Shared Buffer ATM Switch with Fuzzy Controlled Buffer Management,” 1996 IEEE International Conference on Computer Design, pp.149-152.
  93. M.D. Shieh, M.H. Sheu and W.S. Ju, 1996, August, “Low-Power State Assignment for Asynchronous Finite State Machines,” 1996 Midwest Symposium on Circuits and Systems, pp.1325-1328.
  94. M.D. Shieh, M.H. Sheu and Y.C. Hsu, 1996, August, “MAPS: A New and Efficient Block-Matching Criterion for Motion Estimation,” 1996 Midwest Symposium on Circuits and Systems, pp.1393-1396.
  95. M.H. Sheu, M.D. Shieh and S.F. Cheng, 1996, August, “A Unified VLSI Architecture for Decomposition and Synthesis of Discrete Wavelet Transform,” 1996 Midwest Symposium on Circuits and Systems, pp. 113-116.
  96. M.D. Shieh, J.M. Hong and M.H. Sheu, 1996, May, “A CAD System for Automatic Synthesis of Generalized Asynchronous Circuits,” 1996 IEEE International Symposium on Circuits and Systems, vol. 4, pp. 818-821.
  97. M.H. Sheu, S.F. Cheng and M.D. Shieh, 1996, May, “A Pipelined VLSI with Module Structure Design for Discrete Wavelet Transforms,” 1996 International Sysmpium on Circuits and Systems, Vol. 4, pp. 352-355.
  98. C.L. Wey, M.D. Shieh and P.D. Fisher, 1993, October, “ASLCScan: A Scan Design Technique for Asynchronous Sequential Logic Circuits,” IEEE International Conference on Computer Design, pp. 159-162.
  99. M.D. Shieh, C.L. Wey and P.D. Fisher, 1993, August, “Scan Design for Asynchronous Sequential Logic Circuits Using SR-Latches,” 36th Midwest Symposium on Circuits and Systems, pp. 1300-1303.
  100. M.D. Shieh, C.L. Wey and P.D. Fisher, 1992, August, “Model of Asynchronous Finite State Machines and Their Pipelined Structures,” 35th Midwest Symposium on Circuits and Systems, pp. 659-662.
  101. C.L. Wey, M.D. Shieh and P.D. Fisher, 1991, November, “On Synthesis for Testability in Asynchronous Sequential Logic Circuits,” presented at IFIP Workshop on the Relationship Between Synthesis, Test, and Verification, Berkeley.
  102. J.S. Lin, D.W. Yang, T.C. Hsu, S.H. Fang, and M.D. Shieh, 2014, August, “A simplified forward-backward algorithm for reducing memory requirement of non-binary LDPC decoder design,” The 25th VLSI Design/Cad Symposium, pp. 1-2.
  103. J.H. Ye, T.W. Hung and M.D. Shieh, 2013, August, “Low-power Block-based Scalable Montgomery Modular Multiplier,” The 24th VLSI Design/Cad Symposium, pp. 1-2.
  104. W.C. Lin, S. H. Wang, J.H. Ye and M.D. Shieh, 2012, August, “Low-latency Scalable Dual-field Modular Multiplier Based on Radix-4 Montgomery Algorithm,” The 23rd VLSI Design/Cad Symposium, pp. 1-4.
  105. W.C. Lin, J.H. Ye, D.W. Yang, S.Y. Huang, M.D. Shieh and J. Wang, 2011, August, “Look-up Table-based Scissoring for Scanline-based Rendering in OpenVG,” The 22nd VLSI Design/Cad Symposium, pp. 133-136.
  106. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2011, June, “Subspace-based Blind Channel Estimation for CP-free OFDM Systems with Real Symbols,” 2011 Electronic Technology Symposium.
  107. Y.K. Lu and M.D. Shieh, 2010, August, “High-Throughput Re-Encoder Design for Soft-Decision Reed-Solomon Decoding,” The 21st VLSI Design/CAD Symposium, pp. 29-32.
  108. S.H. Fang, J.S. Lin, M.D. Shieh and Y.H. Jen, 2010, August “Design and Implementation of Sort-Free MIMO Detection with Reduced Node Computation,” The 21st VLSI Design/CAD Symposium, pp. 41-44.
  109. J.S. Lin, J.Y. Chen, M.D. Shieh and S.H. Fang, 2010, June, “Low-Complexity Interference Cancellation in Time Domain for Interleaved Uplink OFDMA Systems,” 2010 Electronic Technology Symposium.
  110. W.C. Lin, M.D. Shieh and C.M. Wu, 2009, August, “High-Speed Bit-Serial Divider Design in GF(2m),” The 20th VLSI Design/CAD Symposium.
  111. C.C. Lo, J.G. Luo and M.D. Shieh, 2009, August, “Hardware/Software Exploration for Resource Restricted Real-Time Systems,” The 20th VLSI Design/CAD Symposium.
  112. S.H. Fang, J.Y. Chen, M.D. Shieh and J.S. Lin, 2009, June, “A Subspace-Based Blind Channel Estimation Algorithm for SIMO-OFDM Systems without Cyclic Prefix,” 2009 Electronic Technology Symposium.
  113. C.C. Lo, S.T. Tsai and M.D. Shieh, 2008, August, “A Reconfigurable Architecture for Entropy Decoder and IDCT in H.264,” The 19th VLSI Design/CAD Symposium, pp. S2-4.
  114. C.C. Lo, C.Y. Cho and M.D. Shieh, 2008, August, “A Reconfigurable Architecture for Hybird Motion Estimation,” The 19th VLSI Design/CAD Symposium, pp. S2-5.
  115. J.J. Zhu, F.R. Lee, W.C. Lin and M.D. Shieh, 2008, July, “Software-based Self-test for Digital Signal Processors,” in Proc. 2008 VLSI Test Technology Workshop, pp. 72-77.
  116. W.C. Lin, J.H. Chen and M.D. Shieh, 2007, August, “A Novel Look-up Table-Based Multiplication/Squaring Architecture for Cryptosystems over GF(2m),” The 17th VLSI Design/CAD Symposium.
  117. C.C. Lo, Y.J. Zeng and M.D. Shieh, 2006, August, “Design and Test of a High-Throughput CABAC Encoder,” The 16th VLSI Design/CAD Symposium.
  118. J.H. Chen and M.D. Shieh, 2005, August, “High-Speed Scalar Multiplication for Elliptic Curve Cryptosystems over GF(2m)”, The 15th VLSI Design/CAD Symposium.
  119. J.H. Chen, M.D. Shieh and C.M. Wu, 2004, August, “Modifying Montgomery Inverse Algorithm for High-Speed VLSI Design over GF(2m),” The 14th VLSI Design/CAD Symposium, pp. 199-202.
  120. C.M. Wu, M.D. Shieh, C.H. Wu and Y.T. Hwang, 2003, August, “VLSI Architectural Design Trade-Offs for Sliding-Window Log-MAP Decoder,” The 13th VLSI Design/CAD Symposium.
  121. C.M Wu, M.H. Hu, M.D. Shieh and M.C. Lee, 2002, December, “Design and Implementation of Punctured Viterbi Decoder with Fully Decoding Capability for DAB System”, National Symposium on Telecommunications, COM-8-3. (獲最佳論文獎)
  122. C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2002, December, “High-Speed and Area-Efficient Systolic Division Algorithms in GF(2m) Arithmetic Units for Channel Coding and Cryptography,” National Symposium on Telecommunications, COM-8-2.
  123. C.M. Wu, M.D. Shieh, C.H. Wu and J.Y. Huang, 2001, August, “Exploration of General Memory Structures in Turbo Decoders Using Sliding-Window MAP Algorithm,” The 12th VLSI Design/CAD Symposium, pp. C2-2.
  124. J.C. Ho, M.D. Shieh, S.Y. Lee and C.C. Wang, 2001, August, “Design and Test of Switched-Current Sigma-Delta Modulators,” The 12th VLSI Design/CAD Symposium, pp. A3-13.
  125. H.F. Lo, M.D. Shieh and C.M. Wu, 2000, August, “In-Place Memory Addressing of FFT Hardware Implementation for DAB System,” The 11th VLSI Design/CAD Symposium, pp. 315-318.
  126. C.H. Wu, C.M. Wu, M.D. Shieh and Y.T. Hwang, 2000, August, “VLSI Realization of a Novel Iterative Division Algorithm over GF(2m),” The 11th VLSI Design/CAD Symposium, pp. 187-190.
  127. C.H. Chen, M.D. Shieh and K.S. Hsiao, 2000, August, “VLSI Architecture of an Instruction-Based Crypto Coprocessor,” The 11th VLSI Design/CAD Symposium, pp. 159-162.
  128. M.D. Shieh and H.H. Chou, 1999, August, “On the Test of Algorithmic Switched-Current A/D Converter,” The 10th VLSI Design/CAD Symposium, pp. 179-182.
  129. M.D. Shieh, J.L. Sheu, C.H. Wu and C.H. Wu, 1998, August, “Asynchronous VLSI Architecture of Modular Exponentiation for RSA Cryptosystem,” The 9th VLSI Design/VAD Symposium, pp. 449-452.
  130. J.L. Sheu, M.D. Shieh and C.H. Wu, 1997, August, “A Novel VLSI Architecture for Fast Modular Multiplication,” The 8th VLSI Design/CAD Symposium, pp. 129-132.
  131. M.H. Sheu, M.D. Shieh and S.W. Liu, 1997, August, “An Efficient VLSI Architecture Design for Separate 2-D Discrete Wavelet Transform,” The 8th VLSI Design/CAD Symposium, pp. 121-124.
  132. M.D. Shieh, M.H. Sheu, H.R.Wang and H.C. Cheng, 1996. August, “Reducing the Switching Activity in Asynchronous Circuits for Low Power Dissipation,” The 7th VLSI Design/CAD Symposium, pp. 165-168.
  133. M.H. Sheu, M.D. Shieh, S.W.Liu and C.Dou, 1996, August, “A New System-Level Design Approach by Mapping Graphical SDL to VHDL,” The 7th VLSI Design/CAD Symposium, pp. 171-174.
  134. M.H. Sheu, Y.C. Hsu and M.D. Shieh, 1995, October, “A High Performance VLSI Architecture for the Full Search Black Matching Algorithm,” The First Symposium on Computer and Communication Technology, pp. 149-153.
  135. M.D. Shieh, J.H. Hong, W.T. Jai and M.H. Sheu, 1995, August, “Automating the Design of Generalized Asynchronous Circuits from High-Level Specifications,” The 6th VLSI Design/CAD Symposium, pp. 290-293.
  136. M.H. Sheu, S.F. Cheng and M.D. Shieh, 1995, August, “A Pipelined VLSI Architecture for Discrete Wavelet Transforms,” The 6th VLSI Design/CAD Symposium, pp. 199-202.
  137. 謝明得、王博弘、黃俊傑，1996，三月，“IEEE 1149.1 Boundary Scan 原理探討與架構實現,”第十一屆全國技術及職業教育研討會、工業類電子組，pp. 105-111.
  138. 許嘉麟、宋舜志、謝明得，1996，三月，“高頻鎖相電路之設計與實現,”第十一屆全國技術及職業教育研討會、工業類電子組，pp. 431-435.
Patent
more
less
  1. A PLL with Fast Lock-in Time (ROC pattern I239146)
  2. A Wide-range VCO with Low Input Voltage Control (ROC pattern I230502)
  3. Method for Arranging Memories of Low-Complexity LDPC Decoder and Low-Complexity LDPC Decoder Using the same (ROC pattern I425519)
  4. Auto-contrast enhancement system (ROC pattern I526989)
  5. Gesture recognition system (ROC pattern I539329)
  6. System of image stereo matching (ROC pattern I592901)
  7. ITERATIVE MATCHING METHOD AND SYSTEM FOR PARTIAL FINGERPRINT VERIFICATION (ROC pattern I590170)
  8. Utilization-enhanced Shared Bus System and Bus Arbitration Method (PROC pattern CN102087637 B)
  9. Stereo matching system (PROC pattern CN103986923 B)
  10. Method for Arranging Memories of Low-Complexity LDPC Decoder and Low-Complexity LDPC Decoder Using the same (US pattern US8219879 B2)
  11. System of Image Stereo Matching (US pattern US9171373 B2)
  12. Auto-contrast enhancement system (US pattern US9373162 B2)
  13. Content adaptive compression system (US pattern US9420292 B2)
  14. Utilization-enhanced Shared Bus System and Bus Arbitration Method (ROC pattern pending)
  15. Utilization-enhanced Shared Bus System and Bus Arbitration Method (US pattern pending)
  16. System of Object Detection (US pattern pending)
  17. System of Object Detection (ROC pattern pending)
  18. Gesture recognition system (US pattern pending)
  19. Gesture recognition system (PROC pattern pending)
  20. Method of determining an optimal point in three-dimensional space (US pattern pending)
  21. Iterative matching method and system for partial fingerprint verification (US pattern pending)
  22. 功耗估算方法與功耗估算裝置（中華民國專利, 申請號:106128834, 申請日:2017/08/24）
  23. 適用於疊代最近點法以選擇關鍵圖框的系統與方法（中華民國專利, 申請號：106131250, 申請日期：2017/09/12）
  24. 物件偵測的適應系統與方法（中華民國專利, 申請號：106132087, 申請日期：2017/09/19）
  25. Clustering Method With A Two-Stage Local Binary Pattern And An Iterative Image Testing System Thereof（美國專利, 申請號: 15/272,186, 申請日期: 2016/09/21）
  26. Power Consumption Estimation Method Power Consumption Estimation Apparatus（美國專利, 申請號: 15/853,549, 申請日期: 2017/12/22）
  27. System And Method Of Selecting A Keyframe For Iterative Closet Point（美國專利, 申請號: 15/705,000, 申請日: 2017/09/14）
Others
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less
  1. M.D. Shieh, 1986, May, “High Value of Poly-Resistor Technology for VLSI Applications and A New Model”, M.S. Thesis, Chiao Tung University, Taiwan.
  2. M.D. Shieh, 1993, May, “Design and Synthesis of Testable Asynchronous Sequential Logic Circuits”, Ph. D. dissertation, Michigan State University, U.S.A.
  3. 謝明得、王朝琴，2001，十二月，“電流交換電路之測試”， IC_Design月刊。
  4. 胡閩雄、謝明得、吳建明，2002，三月，“數位廣播新紀元－DAB系統”， e科技雜誌。
  5. 王駿發、謝明得等七位教師，2006年十一月，系統單晶片概論（SOC Design Overview），第五章：矽智產設計簡介，美商麥格羅、希爾（McGraw Hill）。
Projects
  1. Investigation on convolutional and turbo decoding and their VLSI implementations, NSC 89-2215-E-224-015. (1/2)
  2. Investigation on convolutional and turbo decoding and their VLSI implementations, NSC 90-2215-E-224-002. (2/2)
  3. Design and IP creation of high-speed USB/IEEE1394 serial buses, NSC 90-2218-E-224-026.
  4. Advanced research on channel decoders and their VLSI realizations, NSC 91-2215-E-006-030.
  5. Research on automatic synthesis and IP realization of multiple-function channel encoders/decoders, NSC 92-2218-E006-036. (1/2)
  6. Research on automatic synthesis and IP realization of multiple-function channel encoders/decoders, NSC 93-2218-E-006-013. (2/2)
  7. Design and automation of SOC test platform, NSC 93-2220-E-006-007. (1/3)
  8. Research on the design and test of multimedia silicon IPs for SOC, NSC 93-2220-E-006-009. (1/3)
  9. Design and automation of SOC test platform, NSC 94-2220-E-006-007. (2/3)
  10. Research on the design and test of multimedia silicon IPs for SOC, NSC 94-2220-E-006-009. (2/3)
  11. Design and automation of SOC test platform, NSC 94-2220-E-006-007. (3/3)
  12. Research on the design and test of multimedia silicon IPs for SOC, NSC 94-2220-E-006-009. (3/3)
  13. Study and implementation on architectures of high performance soft output channel encoder/decoder, NSC 96-2221-E-006-296-MY3. (1/3)
  14. Development of Electronic System Level (ESL) Design Methodology and its Applications to Multiple-Format SOC Design:ESL-Based Reconfigurable Computing Kernel for Multi-Format Video Codec Applications, NSC 96-2220-E-006-008. (1/3)
  15. Study and implementation on architectures of high performance soft output channel encoder/decoder, NSC 96-2221-E-006-296-MY3. (2/3)
  16. Development of Electronic System Level (ESL) Design Methodology and its Applications to Multiple-Format SOC Design:ESL-Based Reconfigurable Computing Kernel for Multi-Format Video Codec Applications, NSC 96-2220-E-006-008. (2/3)
  17. Study and implementation on architectures of high performance soft output channel encoder/decoder, NSC 96-2221-E-006-296-MY3. (3/3)
  18. Development of Electronic System Level (ESL) Design Methodology and its Applications to Multiple-Format SOC Design:ESL-Based Reconfigurable Computing Kernel for Multi-Format Video Codec Applications, NSC 98-2220-E-006-004. (3/3)
  19. On the design of scalable and reconfigurable high-performance cryptographic processors with resistance to side-channel attacks, NSC 99-2221-E-006-221-MY3. (1/3)
  20. Research and Development of Silicon Debug Platform for SOC Design, NSC 99-2220-E-006-027.
  21. On the design of scalable and reconfigurable high-performance cryptographic processors with resistance to side-channel attacks, NSC 99-2221-E-006-221-MY3. (2/3)
  22. On the design of scalable and reconfigurable high-performance cryptographic processors with resistance to side-channel attacks, NSC 99-2221-E-006-221-MY3. (3/3)
  23. High-performance Joint Iterative Detection and Decoding Design in Coded-MIMO Systems, NSC 102-2221-E-006-273-MY3. (1/3)
  24. High-performance Joint Iterative Detection and Decoding Design in Coded-MIMO Systems, NSC 102-2221-E-006-273-MY3. (2/3)
  25. High-performance Joint Iterative Detection and Decoding Design in Coded-MIMO Systems, NSC 102-2221-E-006-273-MY3. (3/3)
  26. Low-complexity Fully Homomorphic Encryption Processor Design for Secured Cloud Computing, NSC 105-2221-E-006-224-MY3. (1/3)
  27. Low-complexity Fully Homomorphic Encryption Processor Design for Secured Cloud Computing, NSC 105-2221-E-006-224-MY3. (2/3)
  28. Low-complexity Fully Homomorphic Encryption Processor Design for Secured Cloud Computing, NSC 105-2221-E-006-224-MY3. (3/3)
Classes
2023 Fall
2023 Spring
2022 Fall
2022 Spring
2021 Fall
2021 Spring
2020 Fall
2020 Spring
2019 Fall
2019 Spring
2018 Fall
2017 Spring
2016 Fall
2016 Spring
2015 Fall
Students
Current Academic Year Lab Members
Master
Jia-Jun Hu
Wei-Kai Hsu
Yo-Hsuan Chao
Tzyy-Shiuan Yang
Xue-Qian Xiao
Chiu, Ting Chun
Yang, Yue Lin
Li, Tzu Chien
Zheng, Yu Xiang
LIiao, Jun Hao
Liao, Wei Quan
Lu, Bo Cen
Wu, Yan Ting
Fu, I-Chia
Teng, Shu Sian
Li, Chieh
Tsai, Ming Han
Wu, Qi Xian
Graduates of all Previous Years
Master
92
Ming-Shiuan Li    Chung-Guang Li    Chen-Tsung Wu    Tsan-Huei Wu    Jiun-Min Huang    Jeng-Yu Tsai    Shiue-Cheng Jeng
93
Hsiang-An Yu    En-Cheng Lin    Yung-Kuei Lu    Hsiao-Lun Liao    Hain-Nan Hsieh
94
Hsin-Yih Li    Sheng-Hsien Huang    Ying-Jhong Zeng   Guan-Hua Fei
95
Hau-Shiuan Wu    Wen-Ching Lin    Fu-Rong Lee    Sue-Jing Huang
96
Der-Wei Yang    Yi-Lin Tsai    Chao-Yi Cho    Shaun-Da Tsai    Yi-Jun Liu
97
Wen-Hsuen Kuo    Jung-Guan Luo    Shing-Chung Tang    Jun-Jie Zhu
98
Chi-Hsiung Chin    Yi-Hsuan Jen    Yu-Kai Lin   Chia-Wei Hsu
99
Po-Han Chu    Kun-Hsien Lee    Po-Hsun Lin   Si-Yu Huang
100
Sheng-Hong Wang    Wei-Ren W   Chia-Fen Lin    Che-Hao Chang    Chun-Wei Chen
101
Tsung-Chih Hsu   Che-Chia Chang    Szu-Han Huang    Li-Chia Chu   Tsung-Wei Hung    Yun-Sheng Lin    Yun-Chen Chang
102
Chung-Yen Liu    Jia-Ming Gan   Kang-Yu Peng    Ching-Pei Huang
103
Po-Yuan Chiu   Shr-Wei Ho    Ching-Heng Su
104
Pao-Cheng Luo    Fang-Kai Hsu    Tzu-Liang Peng
105
Tzu-Yin Kuo    Ting-Yu Lin    Hsin-Yu Chang    Si-Quan Chen    Chun-Hsien Huang
106
Wen-Yuan Hsiao   Hsiang-Chih Hsiao   Guan-Ying Huang
107
Rong-De Lin   Deng-Feng Laio   Jyun-Neng Ji
108
Yu-Cheng Chen   Hsuan-Jui Hsu   Ji-Ying Li   Yi-Fu Tseng   Tzu-Hsiang Hsu   I-Wei Chen
109
Tzu-Yuan Hsu   Shi-Yong Wu   Wei-Chen Liu
110
Shih-Chun Kao   Wei-Cheng Chen   Jian-Zhi Huang
111
Jian-Zhi Qiu   Chung-Yu Hei   Yao-Hui Su   Cheng-Siang Jheng   Kuan-Yu Chen
Ph.D.
96
Jun-Hong Chen
99
Chia-Chen Lo
100
Tai-ping Wang    Yung-Kuei Lu    Wen-Ching Lin
101
Shih-Hao Fang
103
Jing-Shiun Lin    Der-Wei Yang
104
Hsin-Fu Luo
106
Jheng-Hao Ye
108
Shen-Ming Chung
109
Chun-Wei Chen
Honors
  1. Member, The Phi Tau Phi Scholastic Honor Society, 1984
  2. Teaching Honor, National Yunlin University of Science & Technology, 1998
  3. Course Award, Introduction to VLSI Design, 1987
  4. Course Award, Digital System Testing and Diagnosis, 2000
  5. Technology Transfer and Industrial-Academia Cooperation Awards, National Cheng Kung University, 2010, 2014
  6. The great achievement award from the National Science Council(NSC), Taiwan by Professors Kuen-Jong Lee (principle investigator), Chung-Ho Chen, Ming-Der Shieh, and Soon-Jyh Chang, 2007
  7. Golden Prize, ITRI Excellent Research Awards, 2013
  8. Golden Prize, ITRI Excellent Research Awards, 2014
NCKU EE