NCKUEE Faculty Data
Chinese Version
Assistant Professor Ning-Chi Huang
Address
EE Building 10F R92A03
Email
TEL
+886-6-2757575 ext.62372
Lab
Computer Architecture & Acceleration Techniques Lab
(R92508/ext.62400-1708)
Background
Educations
2022/1/31
Ph.D., Institute of Computer Science and Engineering, Department of Computer Science, National Yang Ming Chiao Tung University, R. O. C.
2016/1/31
B.S., Department of Computer Science, National Chiao Tung University, R. O. C.
Experiences
2026/8/1-current
Assistant Professor, Department of Electrical Engineering, National Cheng Kung University, R. O. C.
2022/5/1-2026/7/31
Postdoctoral Researcher, Department of Computer Science, National Yang Ming Chiao Tung University, R. O. C.
Specialities
  • High-Performance & Low-Power Architecture
  • AI Model Compression & Inference Acceleration
  • Reliability Analysis & Fault-Tolerant System Design
Publication
Journal
more
less
  1. Ning-Chi Huang, Chao-Wei Cheng, and Kai-Chiang Wu, “Timing variability-aware analysis and optimization for variable-latency designs,” IEEE Transactions on Very Large Scale Integration Systems, vol. 30, no. 1, pp. 81-94, Jan. 2022.
Conference
more
less
  1. Wen-Hung Lee, Jian-Jia Chen, Xiaolin Lin, Pei-Shuo Wang, Chi-Chih Chang, Chun-Che Yang, Ning-Chi Huang, Grace Li Zhang, Kai-Chiang Wu, “Dustin: draft-augmented sparse verification for efficient long-context generation with speculative decoding,” in Proc. of International Conference on Machine Learning (ICML), July 2026.
  2. Pei-Shuo Wang, Jian-Jia Chen, Chun-Che Yang, Chi-Chih Chang, Ning-Chi Huang, Mohamed S. Abdelfattah, Kai-Chiang Wu, “Speculate deep and accurate: lossless and training-free acceleration for offloaded llms via substitute speculative decoding,” in Proc. of Conference on Neural Information Processing Systems (NeurIPS), December 2025.
  3. Chih-Ling Chen, Kai-Chiang Wu, Ning-Chi Huang, “Integrating neural architecture search and rematerialization for efficient on-device learning,” in Proc. of Genetic and Evolutionary Computation Conference (GECCO), pp. 1226-1234, July 2025.
  4. Chi-Chih Chang, Wei-Cheng Lin, Chien-Yu Lin, Chong-Yan Chen, Yu-Fang Hu, Pei-Shuo Wang, Ning-Chi Huang, Luis Ceze, Mohamed S. Abdelfattah, Kai-Chiang Wu, “Palu: KV-Cache compression with low-rank projection,” in Proc. of International Conference on Learning Representations (ICLR), pp. 1-28, April 2025.
  5. Endri Taka, Ning-Chi Huang, Chi-Chih Chang, Kai-Chiang Wu, Aman Arora, Diana Marculescu, “Systolic sparse tensor slices: FPGA building blocks for sparse and dense ai acceleration,” in Proc. of ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), pp. 159-171, February 2025.
  6. Ning-Chi Huang, Chi-Chih Chang, Wei-Cheng Lin, Endri Taka, Diana Marculescu, Kai-Chiang Wu, “ELSA: exploiting layer-wise n:m sparsity for vision transformer acceleration,” in Proc. of IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops (CVPRW), pp. 8006-8015, June 2024.
  7. Chi-Chih Chang, Yuan-Yao Sung, Shixing Yu, Ning-Chi Huang, Diana Marculescu, Kai-Chiang Wu; “FLORA: fine-grained low-rank architecture search for vision transformer,” in Proc. of the IEEE/CVF Winter Conference on Applications of Computer Vision (WACV), pp. 2482-2491, January 2024.
  8. Ning-Chi Huang, Min-Syue Yang, Ya-Chu Chang, Kai-Chiang Wu, “Decomposable architecture and fault mitigation methodology for deep learning accelerators,” in Proc. of International Symposium on Quality Electronic Design (ISQED), pp. 1-8, April 2023.
  9. Ning-Chi Huang, Wei-Kai Tseng, Huan-Jan Chou, Kai-Chiang Wu, “An energy-efficient approximate systolic array based on timing error prediction and prevention,” in Proc. of VLSI Test Symposium (VTS), pp. 1-7, April 2021.
  10. Ning-Chi Huang, Yu-Guang Chen, and Kai-Chiang Wu, “Exploration and exploitation of dual timing margins for improving power efficiency of variable-latency designs,” in Proc. of IEEE Symposium on VLSI (ISVLSI), pp. 218-223, July, 2019.
  11. Ning-Chi Huang, Szu-Ying Chen, and Kai-Chiang Wu, “Sensor-based approximate adder design for accelerating error-tolerant and deep-learning applications,” in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 692-697, March 2019.
  12. Chang-Lin Tsai, Chao-Wei Cheng, Ning-Chi Huang, and Kai-Chiang Wu, “Analysis and optimization of variable-latency designs in the presence of timing variability,” in Proc. of Design, Automation and Test in Europe Conference (DATE), pp. 1219-1224, March 2017.
Patent
more
less
Others
more
less
Projects
Classes
2026 Fall
Students
Current Academic Year Lab Members
Master
許朝琳
王君維
李依中
Honors
NCKU EE