NCKUEE Faculty Data
Chinese Version
Associate Professor  Darsen Lu
Address
EE Building 11F R92B09
Email
TEL
+886-6-2757575 ext.62427
Lab Weblink
Semiconductor Device Modeling Lab
(R92C81/ext.62427)
Background
Educations
2011
PhD, University of California, Berkeley, USA
2007
M.S., University of California, Berkeley, USA
2005
B.S., National Tsing Hua University, Taiwan
Experiences
2020/12-present
Associate Professor, National Cheng Kung University, Taiwan
2015/8-2020/12
Assistant Professor, National Cheng Kung University, Taiwan
2011/8-2015/8
Research Scientist, IBM Thomas J. Watson Research Lab, New York, USA
Specialities
  • Process, Measurement, Device design and Circuit model for FinFET Transistor
  • Ferroelectric Memory and Its Applications in Neural Networks/Artificial Intelligence
  • Cryogenic CMOS and Quantum Computing
  • Compact Device Modeling for the FinFET Transistor
  • Compact Device Modeling for UTBB SOI MOSFET
  • Numerical Simulation of Semiconductor Processes and Devices
  • Design and Simulation of Neuromorphic Circuits and Devices
Publication
Journal
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  1. Pei-En Lin, Kuan-Ting Chen, Rajneesh Chaurasiya, Hoang-Hiep Le, Chia-Hao Cheng, Darsen D. Lu, Jen-Sue Chen*, “Bilayered Oxide Heterostructure-Mediated Capacitance-Based Neuroplasticity Modulation for Neuromorphic Classification,” Advanced Functional Materials, pp. 2307961, Sep. 2023, DOI: 10.1002/adfm.202307961.
  2. Ting-Jia Chang, Hoang-Hiep Le, Cheng-Ying Li, Sheng-Yuan Chu* and Darsen Lu*, “HfTaOx rectifying layer for HfOx-based RRAM for high accuracy neuromorphic computing applications,” ACS Applied Electronic Materials, vol. 5, no. 5, pp. 2566-2573, May 2023, DOI: 10.1021/acsaelm.3c00026.
  3. Shu-Wei Chang, Jia-Hon Chou, Wen-Hsi Lee, Yao-Jen Lee and Darsen D. Lu*, “TCAD-Based RF Performance Prediction and Process Optimization of 3D Monolithically Stacked Complementary FET,” Solid State Electronics, vol. 201, p. 108585, Mar. 2023, DOI: 10.1016/j.sse.2022.108585.
  4. Md. Aftab Baig, Cheng-Jui Yeh, Shu-Wei Chang, Bo-Han Qiu, Xiao-Shan Huang, Cheng-Hsien Tsai, Yu-Ming Chang, Po-Jung Sung, Chun-Jung Su, Ta-Chun Cho, Sourav De, Darsen Lu*, Yao-Jen Lee, Wen-Hsi Lee, Wen-Fa Wu, Wen-Kuan Yeh, “3D Monolithic Stacking of Complementary-FET on CMOS for Next Generation Compute-In-Memory SRAM,” IEEE Journal of the Electron Devices Society, vol. 11, pp. 107-113, Dec. 2022, DOI: 10.1109/JEDS.2022.3230542.
  5. Ke-Jing Lee, Yu-Chuan Weng, Li-Wen Wang, Hsin-Ni Lin, Parthasarathi Pal, Sheng-Yuan Chu, Darsen Lu and Yeong-Her Wang*, “High Linearity Synaptic Devices Using Ar Plasma Treatment on HfO2 Thin Film with Non-Identical Pulse Waveforms,” MDPI Nanomaterials, vol. 12, no. 18, p. 3252, Sep. 2022, DOI: 10.3390/nano12183252.
  6. Shu-Wei Chang, Yu-Ming Chang, Wen-His Lee, Yao-Jen Lee, Darsen Lu*, “Nanosheet-Compatible Complementary-FET Logic Non-Volatile Memory Device,” ECS Journal of Solid State Science and Technology, vol. 11, no. 9, Sep. 2022, DOI: 10.1149/2162-8777/ac8dbf.
  7. S. De*, F. Müller, H.-H. Le, M. Lederer, Y. Raffel, T. Ali, D. Lu and T. Kämpfe, “READ-Optimized 28nm HKMG Multi-bit FeFET Synapses for Inference-Engine Applications,” IEEE Journal of the Electron Devices Society, vol. 10, pp. 637-641, Aug. 2022, DOI: 10.1109/JEDS.2022.3195119.
  8. P. Pal, S. Mazumder, C.-W. Huang, D. D Lu and Y.-H. Wang*, “Impact of Barrier Layer on High Thermal and Mechanical Stability of a Flexible Resistive Memory in Neural Network Application,” ACS Applied Electronic Materials, vol. 4, no. 3, Feb. 2022, DOI: 10.1021/acsaelm.1c01219.
  9. Md. A. Baig, H.-H. Le, S. De, C.-W. Chang, C.-C. Hsieh, X.-S. Huang, Y.-J. Lee, D. Lu*, “Compact model of retention characteristics of ferroelectric FinFET synapse with MFIS gate stack,” Semiconductor Science and Technology, vol. 37, no. 2, Feb. 2022, DOI: 10.1088/1361-6641/ac3f22.
  10. S. De*, Md. A. Baig, B.-H. Qiu, F. Müller, H.-H. Le, M. Lederer, T. Kämpfe, T. Ali, P.-J. Sung, C.-J. Su, Y.-J. Lee, D. Lu*, “Random and Systematic Variation in Nanoscale Hf0.5Zr0.5O2 Ferroelectric FinFETs: Physical Origin and Neuromorphic Circuit Implications,” Frontiers in Nanotechnology†, Jan. 26, 2022, DOI: 10.3389/fnano.2021.826232.
  11. S.-W.Chang, T.-H. Lu, C.-Y. Yang, C.-J. Yeh, M.-K. Huang, C.-F. Meng, P.-J. Chen, T.-H. Chang, Y.-S. Chang, J.-W. Jhu, T.-Z. Hong, C.-C. Ke, X.-R. Yu, W.-H. Lu, M. A. Baig, T.-C. Cho, P.-J. Sung, C.-J. Su, F.-K. Hsueh, B.-Y. Chen, H.-H. Hu*, C.-T. Wu, K.-L. Lin, W. C.-Y. Ma, D. D. Lu, K.-H. Kao, Y.-J. Lee*, C.-L. Lin, K.-P. Huang, K.-M. Chen, Y. Li, S. Samukawa, T.-S. Chao, G.-W. Huang, W.-F. Wu, W.-H. Lee, J.-Y. Li, J.-M. Shieh, J.-H. Tarng, Y.-H. Wang*, W.-K. Yeh, “First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3-D Integration with Dual Work Function Gate for Ultralow-Power SRAM and RF Applications,” IEEE Transaction on Electron Devices, vol. 69, no. 4, pp. 2101-2107, Jan. 25, 2022, DOI: 10.1109/TED.2021.3138947.
  12. S. De, H.-H. Le, B.-H. Qiu, Md. A. Baig, P.-J. Sung, C.-J. Su, Y.-J. Lee and D.-D. Lu*, “Robust Binary Neural Network Operation from 233 K to 398 K via Gate Stack and Bias Optimization of Ferroelectric FinFET Synapses,” IEEE Electron Device Letters, vol. 42, no. 8, Aug. 2021, pp. 1144–1147, DOI: 10.1109/LED.2021.3089621.
  13. S. De, B.-H. Qiu, W.-X. Bu, Md. A. Baig, P.-J. Sung, C.-J. Su, Y.-J. Lee and D. D. Lu*, “Uniform Crystal Formation and Electrical Variability Reduction in Hafnium Oxide Based Ferroelectric Memory by Thermal Engineering,” ACS Applied Electronic Materials, vol. 3, no. 2, 2021, pp. 619—628, DOI: 10.1021/acsaelm.0c00610.
  14. W. Lin, D. D. Lu*, Y.-X. Hong and W.-C. Hsu, “Automated Extraction of Barrier Heights for Asymmetric MIM Tunneling Diodes,” Solid State Electronics, vol. 172, no. 107879, Oct. 2020, DOI: 10.1016/j.sse.2020.107879.
  15. D. D. Lu*, S. De, M. A. Baig, B.-H. Qiu and Y.-J. Lee, “A Computationally Efficient Compact Model for Ferroelectric FETs for the Simulation of Online Training of Neural Networks,” Semiconductor Science and Technology, vol. 35, no. 9, Jul. 2020, DOI: 10.1088/1361-6641/ab9bed
  16. P.-J. Sung, C.-J. Su, S.-H. Lo, F.-K. Hsueh, D. D. Lu, Y.-J. Lee*, T.-S. Chao, “Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter,” IEEE Journal of the Electron Devices Society, vol. 8, pp. 474–480, Apr. 2020, DOI: 10.1109/JEDS.2020.2987005.
  17. C.-W. Wang, H. Ku, C.-Y. Chiu, S. De, B.-H. Qiu, C. Shin*, and D. Lu*, “Compact Model for PZT Ferroelectric Capacitors with Voltage Dependent Switching Behavior,” Semiconductor Science and Technology, vol 35, no. 5, Apr. 2020, DOI: 10.1088/1361-6641/ab7c79.
  18. S.-H. Chen, S.-W. Lian, T. R. Wu, T.-R. Chang, J.-M. Liou, D. D. Lu, K.-H. Kao*, N.-Y. Chen, W.-J. Lee and J.-H. Tsai, “Impact of Semiconductor Permittivity Reduction on Electrical Characteristics of Nanoscale MOSFETs,” IEEE Transaction on Electron Devices, vol. 66, no. 6, pp. 2509–2512, Jun. 2019, DOI: 10.1109/TED.2019.2912058.
  19. Y.-F. Hsieh*, S.-H. Chen, N.-Y. Chen, W.-J. Lee, J.-H. Tsai, C.-N. Chen, M.-H. Chiang, D. D. Lu and K.-H. Kao*, “An FET With a Source Tunneling Barrier Showing Suppressed Short-Channel Effects for Low-Power Applications,” IEEE Transaction on Electron Devices, vol. 65, no. 3, pp. 855–850, Mar. 2018, DOI: 10.1109/TED.2018.2791467.
  20. A. B. Sachid*, Y.-M. Huang, Y.-J. Chen, C.–C. Chen, D. D. Lu, M.-C. Chen, C. Hu, “FinFET with Encased Air-Gap Spacers for High-Performance and Low-Energy Circuits,” IEEE Electron Device Letters, vol. 38, no. 1, pp. 16-19, Jan 2017, DOI: 10.1109/LED.2016.2628768.
  21. Q. Cao*, S. J. Han, G. S. Tulevski, Y. Zhu, D. D. Lu, W. Haensch, “Arrays of single-walled carbon nanotubes with full surface coverage for high-performance electronics.” in Nature Nanotechnology, 8(3), pp. 180-186, 2013, DOI:10.1038/NNANO.2012.257.
  22. R. Muralidhar*, J. Cai*, D. J. Frank*, P. Oldiges*, D. Lu*, and I. Lauer*, “Meeting the Challenge of Multiple Threshold Voltages in Highly Scaled Undoped FinFETs,” IEEE Transaction on Electron Devices, vol 60, issue 3, pp. 1276-1278, Mar 2013, DOI: 10.1109/TED.2013.2241767.
  23. S. J. Han*, S. Oida, K. A. Jenkins, D. Lu and Y. Zhu, “Multifinger Embedded T-shaped Gate Graphene RF Transistors with High fMAX/fT Ratio,” IEEE Electron Device Letters, vol. 34, no. 10, pp. 1340-1342, Oct. 2013, DOI: 10.1109/LED.2013.2276038.
  24. M. A. Karim, Y.-S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, et al., “Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs,” IEEE Electron Device Letters, vol. 33, pp. 1306-1308, Sep 2012, DOI: 10.1109/LED.2012.2205659
  25. S. Khandelwal, Y. S. Chauhan, D. D. Lu, et al., “BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control,” IEEE Tran. on Electron Devices, vol 59, issue 8, pp. 2019-2026, 2012，DOI: 10.1109/TED.2012.2198065.
  26. S. Venugopalan, D. D. Lu, Y. Kawakami, P. M. Lee, A. M. Niknejad and C. Hu, “BSIM-CG: A compact model of cylindrical/surround gate MOSFET for circuit simulations,” Solid-state Electronics, 67(1), 79-89, 2012, DOI: 10.1016/j.sse.2011.09.001.
  27. D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, “A Computationally Efficient Compact Model for Fully-Depleted SOI MOSFETs with Independently Controlled Front- and Back-Gates,” Solid State Electronics, vol. 62, issue 1, pp. 31-39, Aug 2011, DOI: 10.1016/j.sse.2010.12.015.
  28. D. D. Lu, C.-H. Lin, A. M. Niknejad and C. Hu, “Compact Modeling of Variation in FinFET SRAM Cells,” IEEE Design and Test of Computers, vol. 27, no. 2, Mar/Apr 2010, DOI: 10.1109/MDT.2010.39.
  29. C.-H. Lin, M. V. Dunga, D. D. Lu, A. M. Niknejad, and C. Hu, "Performance-Aware Corner Model for Design for Manufacturing," IEEE Transaction on Electron Devices, vol, 56, no. 4, April. 2009, DOI: 10.1109/TED.2008.2011845.
  30. M. V. Dunga, C.-H. Lin, X. Xi, D. D. Lu, A. M. Niknejad, and C. Hu, "Modeling Advanced FET Technology in a Compact Model," IEEE Transaction on Electron Devices, vol. 53, no. 9, Sept. 2006, DOI: 10.1109/TED.2005.881001.
Conference
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  1. Woan- Jen, Hsiao, Tetsuya Asai, Darsen Lu and Kota Ando*, “A Novel Near-memory Computing Architecture for Recurrent Neural Networks,” International Symposium on Neuromorphic AI Hardware, Kitakyushu, Japan, Mar 2024.
  2. X.-R. Yu, C.-C. Hsieh, M.-H. Chuang, M.-Y. Chiu, T.-C. Sun, W.-Z. Geng, W.-H. Chang, Y.-J. Shih, W.-H. Lu, W.-C. Chang, Y.-C. Lin, Y.-C. Pai, C.-Y. Lai, M.-H. Chuang, Y. Dei, C.-Y. Yang, H.-Y. Lu, N.-C. Lin, C.-T. Wu, K.-H. Kao, W. C.-Y. Ma, D. D. Lu, Y.-J. Lee*, G.-L. Luo, M.-H. Chiang, T. Maeda, W.-F. Wu, Y.-M. Li**, T.-H. Hou, Y.-H. Wang, “First Demonstration of Defect Elimination for Cryogenic Ge FinFET CMOS Inverter Showing Steep Subthreshold Slope by Using Ge-on-Insulator Structure,” IEEE International Electron Devices Meeting (IEDM), Dec. 2023.
  3. Md. Aftab Baig, Hao Yu Lu, Cheng Hsien Tsai, Wei Chen Hung, Hoang Hiep Le, Sourav De, Nan Yow Chen, Wen Jay Lee, Ing Chao Lin, Da Wei Chang, Darsen Lu,” Analyzing the Effects of Non-Ideal Synaptic Devices on Computing-in-Memory with Online Training Using the Accumulated Weight Update Algorithm,” International Electron Devices and Materials Symposium (IEDMS), Kaohsiung, Taiwan, Oct. 2023.
  4. W.-C. Lin, H.-P. Huang, K.-H. Kao, M.-H. Chiang, D. Lu, W.-C. Hsu, Y.-H. Wang, W.C.-Y. Ma, H.-H. Tsai, Y.-J. Lee, H.-L. Chiang, J.-F. Wang and I. Radu, “MOSFET Characterization with Reduced Supply Voltage at Low Temperatures for Power Efficiency Maximization,” ESSDERC 2023, Lisbon, Portugal, pp. 9-12, Sep. 2023, DOI: 10.1109/ESSDERC59256.2023.10268514
  5. (Invited) Darsen D. Lu*, “Computing-in-Memory with Ferroelectric Materials and Beyond,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2023, DOI: 10.1109/VLSI-TSA/VLSI-DAT57221.2023.10133993
  6. C.-Y. Yang, P.-J. Sung*, M.-H. Chuang, C.-W. Chang, Y.-J. Shih, T.-Y. Huang, D. D. Lu*, T.-C. Hong, X.-R. Yu, W.-H. Lu, S.-W. Chang, J.-J. Tsai, M.-K. Huang, T.-C. Cho, Y.-J. Lee*, K.-L. Luo, C.-T. Wu, C.-J. Su, K.-H. Kao, T.-S. Chao, W.-F. Wu, Y.-H. Wang*, “First Demonstration of Heterogeneous L-shaped Field Effect Transistor (LFET) for Angstrom Technology Nodes,” IEEE International Electron Devices Meeting, Dec. 2022, DOI: 10.1109/IEDM45625.2022.10019487.
  7. Shu-Wei Chang, Jia-Hon Chou, Wen-Hsi Lee, Yao-Jen Lee and Darsen D. Lu*, “Process TCAD for RF Performance Step-Up of Three-dimensional Stackable Complementary FET and Improvement Suggestions, “International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Granada, Spain, Sep. 6-8, 2022.
  8. X.-R. Yu, W.-H Chang*, T.-C. Hong, P.-J. Sung, A. Agarwal, G.-L. Luo, C.-T. Wu, K.-H. Kao, C.-J. Su, S.-W. Chang, W.-H. Lu, W.-J. Chen, P.-Y. Fu, J.-H. Lin, P.-H. Wu, T.-C. Cho, W. C.-Yu. Ma, D.-D. Lu, R.W. Chuang, T.-S. Chao, T. Maeda, Y.-J. Lee*, W.-F. Wu, W.-K. Yeh, Y.-H. Wang*, “First Demonstration of Vertical Stacked Hetero-Oriented n-Ge (111)/p-Ge (100) CFET toward Mobility Balance Engineering,” Proc. IEEE Symposium on VLSI Technology, pp. 399-400, Honolulu, HI, USA, Jun. 2022, DOI: 10.1109/VLSITechnologyandCir46769.2022.9830316.
  9. S. De, Md. A. Baig, B.-H. Qiu, H.-H. Le, Y.-J. Lee* and D. Lu*, “Neuromorphic Computing with Fe-FinFETs in the Presence of Variation,” VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2022, DOI: 10.1109/VLSI-TSA54299.2022.9771015.
  10. S.-W.Chang, T.-H. Lu, C.-Y. Yang, C.-J. Yeh, M.-K. Huang, C.-F. Meng, P.-J. Chen, T.-H. Chang, Y.-S. Chang, J.-W. Jhu, T.-Z. Hong, C.-C. Ke, X.-R. Yu, W.-H. Lu, M. A. Baig, T.-C. Cho, P.-J. Sung, C.-J. Su, F.-K. Hsueh, B.-Y. Chen, H.-H. Hu*, C.-T. Wu, K.-L. Lin, W. C.-Y. Ma, D.-D. Lu, K.-H. Kao, Y.-J. Lee*, C.-L. Lin, K.-P. Huang, K.-M. Chen, Y. Li, S. Samukawa, T.-S. Chao, G.-W. Huang, W.-F. Wu, W.-H. Lee, J.-Y. Li, J.-M. Shieh, J.-H. Tarng, Y.-H. Wang*, W.-K. Yeh, “First Demonstration of Heterogeneous IGZO/Si CFET Monolithic 3D Integration with Dual Workfunction Gate for Ultra Low-power SRAM and RF Applications,” Proc. IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, Dec. 13-15, 2021, DOI: 10.1109/IEDM19574.2021.9720675.
  11. Szu-Han Hu, Min-Jung Tsai, Fang-Rong Zhang, Ke-Jing Lee, Dar-Sen Lu, Ting-Chang Chang, Yeong-Her  Wang*, “Stacked Three-dimensional Crossbar Resistive Random Access Memory based Synapse for Neuromorphic Computing, “International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, Nov. 2021.
  12. Min-Jung Tsai, Szu-Han Hu, Chih-Wei Hunag, Ke-Jing Lee, Darsen Lu, Ting-Chang Chang, Yeong-Her Wang*, “HfO2 and TiO2 Stacking Resistive Random Access Memory Structure for Neuromorphic Synapse Applications,“ International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, Nov. 2021.
  13. Parthasarathi Pal, Chih-Wei Huang, Darsen Lu, Yeong-Her Wang*, “High Temperature Stability of A Flexible Stacked Resistive Memory Device in the Deep Neural Network Application,” International Electron Devices and Materials Symposium (IEDMS), Tainan, Taiwan, Nov. 2021.
  14. Parthasarathi Pal, Fang-Rong Zhang, Darsen D. Lu, and Yeong-Her Wang*, “Effect of an Interfacial layer on the Thermal and Mechanical Stability of a Heterogeneous Flexible Resistive Switching Device in the Deep Neural Network Simulations,” The 9th International Conference on Science, Education, and Viable Engineering (ICSEVEN), Taitung, Taiwan, Oct. 2021.
  15. D. D. Lu* and I.-H. Chen, “A Novel Three-Dimensional 6T-SRAM Cell Featuring Vertical Transistors and 24F2 Layout Area,” IEEE Intl. Conf. on App. Science & Innovation (ICASI), Alishan, Chiayi, Taiwan, Sep. 2021, DOI: 10.1109/ICASI52993.2021.9568447.
  16. S. De*, D. D. Lu*, H.-H. Le, S. Mazumder, Y.-J. Lee*, W.-C. Tseng, B.-H. Qiu, Md. A. Baig, P.-J. Sung, C.-J. Su, C.-T. Wu, W.-F. Wu, W.-K. Yeh, Y.-H. Wang, “Ultra-Low Power Robust 3bit/cell Hf0.5Zr0.5O2 Ferroelectric FinFET with High Endurance for Advanced Computing-In-Memory Technology,“ Proc. Symposium on VLSI Technology, Kyoto, Japan, Jun. 13-19, 2021.
  17. Pei-En Lin, Chia-Hao Cheng, Ching-Hsiang Chang, Cheng-Hsien Tsai, Darsen D. Lu, Yi-Ting Tseng, Ting-Chang Chang, Jen-Sue Chen, “Electroforming-free resistive switching of WOx/ZrOx stack for neuromorphic computing systems,” Materials Challenges for Memory (MCFM), Apr. 11-13, 2021.
  18. S. De*, W.-X. Bu, B.-H. Qiu, C.-J. Su, Y.-J. Lee and D. D. Lu*, “Alleviation of Charge Trapping and Flicker Noise in HfZrO2-Based Ferroelectric Capacitors by Thermal Engineering,” IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2021, DOI: 10.1109/VLSI-TSA51926.2021.9440091.
  19. J.-Y. Ciou, S. De*, C.-W. Wang, W. Lin, Y.-J. Lee and D. Lu*, “Analytical Modelling of Ferroelectricity Instigated Enhanced Electrostatic Control,” 5th IEEE Electron Devices Technology & Manufacturing Conference (EDTM), Chengdu, China, Apr. 2021, DOI: 10.1109/EDTM50988.2021.9420931.
  20. T.-Z. Hong, W.-H. Chang*, A. Agarwal, Y.-T. Huang, C.-Y. Yang, T.-Y. Chu, H.-Y. Chao, Y. Chuang, S.-T. Chung, J.-H. Lin, S.-M. Luo, C.-J. Tsai, M.-J. Li, X.-R. Yu, N.-C. Lin, T.-C. Cho, P.-J. Sung*, C.-J. Su, G.-L. Luo, F.-K. Hsueh, K.-L. Lin, H. Ishii, T. Irisawa, T. Maeda, C.-T. Wu, W. C.-Y. Ma, D.-D. Lu, K.-H. Kao, Y.-J. Lee*, H. J.-H. Chen, C.-L. Lin, R. W. Chuang, K.-P. Huang, S. Samukawa, Y.-M. Li, J.-H. Tarng, T.-S. Chao, M. Miura, G.-W. Huang, W.-F. Wu, J.-Y. Li, J.-M. Shieh, Y.-H. Wang, W.-K. Yeh, “First Demonstration of heterogenous Complementary FETs utilizing Low-Temperature (200 °C) Hetero-Layers Bonding Technique (LT-HBT),” Proc. IEEE International Electron Devices Meeting (IEDM), Dec. 2020, DOI: 10.1109/IEDM13553.2020.9372001.
  21. S. De, Md. A. Baig, B.-H. Qiu, D. Lu*, P.-J. Sung, F.-K. Hsueh, Y.-J. Lee, C.-J. Su, “Tri-Gate Ferroelectric FET Characterization and Modelling for Online Training of Neural Networks at Room Temperature and 233K,” IEEE Device Research Conference (DRC), Ohio State University, Ohio, USA, Jun. 2020, DOI: 10.1109/DRC50226.2020.9135186.
  22. H.-H. Le, W.-C. Hong, J.-W. Du, T.-H. Lin, Y.-X. Hong, I-H. Chen, W.-J. Lee, N.-Y. Chen and D. D. Lu*, “Ultralow Power Neuromorphic Accelerator for Deep Learning Using Ni/HfO2/TiN Resistive Random Access Memory,” 4th IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020, DOI: 10.1109/EDTM47692.2020.9117915.
  23. S.-W. Chang, P.-J. Sung, T.-Y. Chu, D. D. Lu et al., “First Demonstration of CMOS Inverter and 6T-SRAM Based on GAA CFETs Structure for 3D-IC Applications,” Proc. IEEE International Electron Devices Meeting (IEDM), 2019, DOI: 10.1109/IEDM19573.2019.8993525.
  24. P. J Sung, C. J. Su, D. D. Lu et al., “Fabrication of Ω-gated Negative Capacitance FinFETs and SRAM,” VLSI Technology, Systems and Applications (VLSI-TSA), 2019, DOI: 10.1109/VLSI-TSA.2019.8804663.
  25. D. D. Lu et al., “(Invited) Compact Device Models for FinFET and Beyond,” Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices (AWAD) Tech. Dig., Kitakyushu, Japan, July 2018, arXiv:2005.02580.
  26. D. D. Lu, F.-X Liang, Y.-C. Wang and H.-K. Zeng, “NVMLearn: A Simulation Platform for Non-Volatile-Memory-Based Deep Learning Hardware,” IEEE Intl. Conf. on App. Science & Innovation (ICASI), Sapporo, Japan, May 2017, DOI: 10.1109/ICASI.2017.7988347. (First Prize Paper Award)
  27. D. D. Lu, A. B. Sachid, Y.-M. Huang, Y.-J. Chen, C.-C. Chen, M.-C. Chen, C. Hu, “Stressor Design for FinFETs with Air-Gap Spacers,” VLSI Technology, Systems and Applications (VLSI-TSA), Apr. 2017, DOI: 10.1109/VLSI-TSA.2017.7942485.
  28. T. Yamashita, S. Mehta, V.S. Basker, R. Southwick, A. Kumara, R. Kambhampatib, R. Sathiyanarayanana, J. Johnsona, T. Hook, S. Cohen, J. Li, A. Madan, Z. Zhu, L. Tai, Y. Yao, P. Chinthamanipeta, M. Hopstaken, Z. Liu, D. Lu et al., “A Novel ALD SiBCN Low-k Spacer for Parasitic Capacitance Reduction in FinFETs,” Symposium on VLSI Technology, Digest of Technical Papers, June 2015, DOI: 10.1109/VLSIT.2015.7223659.
  29. P. Morin, L. Grenouillet, N. Loubet, A. Pofelski, D. Lu et al., “Mechanical analyses of extended and localized UTBB stressors formed with Ge enrichment techniques,” ECS Transactions, vol. 66, no. 4, pp. 57-65, 2015, DOI: 10.1149/MA2015-01/21/1364.
  30. D. Lu, K. Cheng, P. Morin, N. Loubet, T. Hook, and D. Guo et al., “Dielectric Isolated FinFET on Bulk Substrate,” IEEE S3S conference, Oct. 2014, DOI: 10.1109/S3S.2014.7028188.
  31. D. Lu, P. Morin, B. Sahu, T. B. Hook, P. Hashemi and A. Scholze et al., “(Invited) Silicon Germanium FinFET Device Physics, Process Integration and Modeling Considerations,” ECS Transactions, vol. 64, no. 6, pp. 337-345, 2014, DOI: 10.1149/06406.0337ecst.
  32. K. Cheng, S. Seo, J. Faltermeier, D. Lu et. al., “Bottom Oxidation through STI (BOTS) – A Novel Approach to Fabricate Dielectric Isolated FinFET on Bulk Substrates,” Symposium on VLSI Technology, Digest of Technical Papers, June 2014, DOI: 10.1109/VLSIT.2014.6894390.
  33. S.-J. Han, S. Oida, K. A. Jenkins, D. D. Lu, "High fMAX/fT ratio in multi-finger embedded T-shaped gate graphene transistors, " IEEE Device Research Conference, 2013, DOI: 10.1109/DRC.2013.6633781.
  34. A. Khakifirooz, R. Sreenivasan, B.N. Taber, F. Allibert, P. Hashemi, W. Chern, N. Xu, E.C. Wall, S. Mochizuki, J. Li, Y. Yin, N. Loubet, A. Reznicek, S.M. Mignot, D. Lu et. al., “Aggressively Scaled Strained Silicon Directly on Insulator (SSDOI) FinFETs,” Proceedings of the S3S Conference, pp. 147-150, 2013, DOI: 10.1109/S3S.2013.6716520.
  35. D. D. Lu, J. Chang, M. A. Guillorn, C.-H. Lin, J. Johnson, P. Oldiges and K Rim, “A comparative study of fin-last and fin-first SOI FinFETs,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept. 2013，DOI: 10.1109/SISPAD.2013.6650596.
  36. D. Lu, C.-H. Lin, A. Niknejad and C. Hu, “Multi-Gate MOSFET Compact Model BSIM-MG,” a chapter in Compact Modeling Principles, Techniques, and Applications (ISBN: 978-90-481-8613-6), Springer, 2010, DOI: 10.1007/978-90-481-8614-3_13.
  37. T. H. Morshed, M. V. Dunga, J. Zhang, D. D. Lu, A. M. Niknejad and C. Hu, "Compact Modeling of Flicker Noise Variability in Small Size MOSFETs," International Electron Device Meeting (IEDM), Dec. 2009, DOI: 10.1109/IEDM.2009.5424237.
  38. D. D. Lu, C.-H. Lin, S. Yao, W. Xiong, F. Bauer, C. R. Cleavelin, A. M. Niknejad, and C. Hu, “Design of FinFET SRAM Cells using a Statistical Compact Model,” International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Sept. 2009, DOI: 10.1109/SISPAD.2009.5290234.
  39. C.-H. Lin, M. V. Dunga, D. Lu, A. M. Niknejad and C. Hu, ”Statistical Compact Modeling of Variations in Nano MOSFETs,” Proc. VLSI Technology, Systems and Applications (VLSI-TSA), Oct 2008, DOI: 10.1109/VTSA.2008.4530849.
  40. D. D. Lu, M. V. Dunga, C.-H. Lin, A. M. Niknejad and C. Hu, ”A Multi-Gate MOSFET Compact Model Featuring Independent-Gate Operation,” International Electron Device Meeting (IEDM), Dec. 2007, DOI: 10.1109/IEDM.2007.4419001.
  41. M. V. Dunga, C.-H. Lin, D. D. Lu, W. Xiong, C. R. Cleavelin, P. Patruno, J.-R. Huang, F.-L. Yang, A. M. Niknejad, and C. Hu, “BSIM-MG: A versatile multi-gate FET model for mixed-signal design,” Symposium on VLSI Technology, June 2007, DOI: 10.1109/VLSIT.2007.4339727. (Best Student Paper Award)
Patent
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  1. Y. Wang, D. Guo, D. Lu, P. J. Oldiges, G. Wang, X. Wang, “Method and structure for dielectric isolation in a fin field effect transistor,” US patent #9,034,715, May 19, 2015
  2. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, “Engineered substrate and device for co-integration of strained silicon and relaxed silicon,” US patent #9,209,065, Dec. 8, 2015
  3. Kangguo CHENG Tenko Yamashita Darsen D. Lu Xin Miao. FinFET with reduced parasitic capacitance. US9786737B2 12/13/2015
  4. Chung H. Lam Philip J. Oldiges CHUNG-HSUN LIN Darsen D. Lu. FinFET PCM access transistor having gate-wrapped source and drain regions. US9825094B2 11/30/2015
  5. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, K. Rim, “Structure and method to make strained FinFET with improved junction capacitance and low leakage,” US patent #9,276,113, #9,653,541, Mar. 1, 2016
  6. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek and K. Rim, “Structure and method for advanced bulk fin isolation,” US patent #9,299,618, #9,564,439, #9,583,492, Mar. 29, 2016
  7. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek and K. Rim, “Semiconductor device including dielectrically isolated finFETs and buried stressor,” US patent #9,362,400, Jun. 7, 2016
  8. K. Cheng, A. Khakifirooz, D. D. Lu, G. Shahidi, “Distributed decoupling capacitor,” US patent #9,455,250, #10,262,991, Sep. 27, 2016
  9. B. B. Doris, A. Khakifirooz, D. D. Lu, P. Oldiges, “Radiation tolerant device structure,” US patent #9,515,171, Dec. 6, 2016.
  10. P. Hashemi, A. Khakifirooz, D. Lu, A. Reznicek, D. Schepis, “Lateral bipolar junction transistor having graded SiGe base,” US patent #9,525,027, Dec. 20, 2016
  11. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, K. Rim, “Strain release in pFET regions,” US patent #9,543,323, #9,761,610, #9,966,387, Jan. 10, 2017
  12. K. Cheng, B. B. Doris, A. Khakifirooz, D. D. Lu, A. Reznicek, K. Rim, “Structure and method for compressively strained silicon germanium fins for pFET devices and tensily strained silicon fins for nFET devices,” US patent #9,548,386, #9,997,540, Jan. 17, 2017
  13. K. Cheng, B. B. Doris, D. D. Lu, A. Khakifirooz, K. Rim, “Dielectrically isolated fin with improved fin profile,” US patent #9,548,213, #9,917,188, Jan. 17, 2017.
  14. C. H. Lam, C.-H. Lin, D. D. Lu, P. J. Oldiges, “Asymmetric FinFET memory access transistor,” US patent #9,553,173, #9,583,624, Jan. 24, 2017
  15. K. Cheng, T. Yamashita, D. D. Lu, X. Miao, “FinFET with reduced parasitic capacitance,” US patent #9,786,737, #10,177,223, Oct. 10, 2017
  16. C. H. Lam, P. J. Oldiges, C.-H. Lin, D. D. Lu, “FinFET PCM access transistor having gate-wrapped source and drain regions,” US patent #9,825,094, 9,825,094, Nov. 21, 2017
  17. K. Cheng, D. D. Lu, A. Reznicek, B. B. Doris, A. Khakifirooz, K. Rim, “Semiconductor structures having increased channel strain using fin release in gate regions,” US patent #9,954,083, #10,056,474, #10,347,752, Apr. 24, 2018
  18. D. D. Lu, Y.-C. Wang and H.-K. Zeng, “Flash memory with multiple control gates and flash memory array device made thereof,” US patent #10,622,451, Apr 14, 2020.
  19. Darsen Duane Lu and Chi-Jen Lin, “Ferroelectric Memory and Memory Array Device with Multiple Independently Controlled Gates,” Taiwan patent #I760122, Apr. 1, 2022
  20. Darsen Duane Lu and Chi-Jen Lin, “Ferroelectric Memory and Memory Array Device with Multiple Independently Controlled Gates,” US patent #11,785,778 B2, Oct. 10, 2023.
Others
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  1. W.-S. Khwa, D. Lu, C. Dou, and M.-F. Chang, “Emerging NVM Circuit Techniques and Implementations for Energy-Efficient Systems,” a chapter in Beyond-CMOS Technologies for Next Generation Computer Design (ISBN: 978-3-319-90385-9), Springer International Publishing, Jan. 2018, DOI: 10.1007/978-3-319-90385-9_4
  2. Y.-S. Chauhan, D. Lu, S. Venugopalan, S. Khandelwal, J. P. Duarte, N. Paydavosi, A. Niknejad and C. Hu, FinFET Modeling for IC Simulation and Design,” Elsevier, 2015.
  3. D. D. Lu, C.-H. Lin, A. M. Niknejad and C. Hu, “Multi-Gate MOSFET Compact Model BSIM-MG,” a chapter in “Comapct Modeling Principles, Techniques and Applications,” Springer, 2010.
Projects
Classes
2023 Fall
2022 Fall
2022 Spring
2021 Fall
2021 Spring
2020 Fall
2020 Spring
2019 Fall
2019 Spring
2018 Fall
2018 Spring
2017 Fall
2017 Spring
Students
Current Academic Year Lab Members
Ph.D.
Hao Yu, Lu
Graduates of all Previous Years
Ph.D.
110
SOURAV DE
111
MD Aftab Baig
Master
105
CHEN,YI-SYUAN
107
HONG,YI-SIOU   WANG,CHIEN-WEI   WANG,YI-JI   CIOU,JHENG-YAN    DU,JIAN-WEI   LIN,ZONG-HAN   ZENG,HUAI-KUAN
108
LIANG,FU-SIANG   HONG,WEI-CHEN
Honors
  1. Who is who in America 2016
  2. UC Berkeley EECS Department Fellowship, Aug 2005
  3. Phi Tau Phi scholastic honor society, June 2005
NCKU EE