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A. Referred Paper (21)
IEEE Transactions and ACM papers (12)
- Yi-Ying Tsai and Chung-Ho Chen,
Energy-efficient Trace
Reuse Cache for Embedded Processor,
IEEE Transactions on Very Large Scale Integration
Systems,
Vol. 19, No. 9, pp. 1681-1694, September 2011. (SCI, EI)
- Tai-Hua Lu, Chung-Ho Chen, and
Kuen-Jong Lee,
Effective Hybrid Test
Program Development for Software-Based Self-Testing of Pipeline
Processor Cores,
IEEE Transactions on Very Large Scale Integration
Systems,
Vol. 19, No. 3, pp. 516-520, March 2011. (SCI, EI)
- Wei-Cheng Lin and Chung-Ho Chen,
Frame Buffer Access
Reduction for MPEG Video Decoder,
IEEE Transactions on Circuits and Systems for
Video Technology,
Vol. 18, No. 10, pp. 1452-1456, October 2008. (SCI, EI)
- Chung-Ming Chen and Chung-Ho Chen,
Configurable VLSI
Architecture for Deblocking Filter in H.264/AVC,
IEEE Transactions on Very Large Scale Integration
Systems,
Vol. 16, No. 8, pp. 1072-1082, August 2008. (SCI, EI)
- Chung-Ho Chen and Kuo-Su Hsiao,
Scalable Dynamic
Instruction Scheduler through Wakeup Spatial Locality,
IEEE Transactions on Computers,
Vol. 56, No. 11, pp. 1534-1548, November 2007. (SCI, EI)
- Chung-Ho Chen, Chih-Kai Wei,
Tai-Hua Lu, and Hsun-Wei Gao,
Software-Based
Self-Testing with Multiple-Level Abstractions for Soft Processor Cores,
IEEE Transactions on Very Large Scale Integration
Systems,
Vol. 15, No. 5, pp. 505-517, May 2007. (SCI, EI)
- Kuo-Su Hsiao and Chung-Ho Chen,
Wake-Up Logic
Optimizations Through Selective Match and Wakeup Range Limitation,
IEEE Transactions on Very Large Scale Integration
Systems,
Vol. 14, No. 10, pp. 1089-1102, October 2006. (SCI, EI)
- C. -H. Chen and F.-F Lin,
An Easy-to-Use Approach
for Practical Bus-Based System Design,
IEEE Transactions on Computers,
Vol. 48, No. 8, pp. 780-793, August 1999. 國科會甲種研究獎 (SCI,
EI)
- C. -H. Chen and A. K. Somani,
Fault-Containment in
Cache Memories for TMR Redundant Processor Systems,
IEEE Transactions on Computers,
Vol. 48, No. 4, pp. 386-39, April 1999. 國科會甲種研究獎 (SCI,
EI)
- C. -H. Chen and A. K. Somani,
Architecture Technique
Trade-Offs Using Mean Memory Delay Time,
IEEE Transactions on Computers,
Vol. 45, No. 10, pp. 1089-1100, October 1996. 國科會甲種研究獎 (SCI,
EI)
- Craig M. Wittenbrink, A. K. Somani, and C.
-H. Chen,
Cache Write Generate for
Parallel Image Processing on Shared Memory Architectures,
IEEE Transactions on Image Processing,
Vol. 5, No. 7, pp. 1204-1208, July 1996. (SCI, EI)
- C. -H. Chen and A. K. Somani,
A Unified Architectural
Tradeoff Methodology,
ACM SIGARCH Computer Architecture News,
Vol. 22, Iss. 2, pp. 348-357, April 1994.
Other Journals (9)
- Chung-Ming Chen and Chung-Ho Chen,
Window Architecture for
Deblocking Filter in H.264/AVC,
International Journal of Innovative Computing,
Information and Control ,
Vol. 3, No. 6, pp. 1677-1695, December 2007. (SCI, EI)
- Chung-Ho Chen, Chao-Hsien Hsu,
and Chen-Chieh Wang,
Scalable IPv6
Lookup/Update Design for High-Throughput Routers,
Journal of Internet Technology,
Vol. 8, No. 3, pp. 261-269, July 2007. (EI)
- Chung-Ming Chen and Chung-Ho Chen,
An Efficient Pipeline
Architecture for Deblocking Filter in H.264/AVC,
IEICE Transactions on Information and Systems,
Vol. E90-D, No.1 pp.99-107, January 2007. (SCI, EI)
- M.-D. Shieh, M.-H. Sheu, C.-H. Chen
, and H.-F. Lo
A Systematic Approach for
Parallel CRC Computations,
Journal of Information Science and Engineering,
Vol. 17, No. 3, pp. 445-461, May 2001. (SCI)
- C.-H. Chen and Akida Wu,
Address Prediction Using
a Bit-Matrix Indexing Scheme for Selective Update,
Journal of Computers,
Vol. 12 No.3, September 2000.
- C.-H. Chen and Akida Wu,
Performance Evaluation of
Load/Store Issue and Memory Access Policies,
Journal of the Chinese Institute of Engineers,
Vol.23, No. 6, pp. 697-709, 2000. (SCI, EI)
- C. -H. Chen,
Exploring the Design
Space of Cache Memories, Bus Width, and Burst Transfer Memory Systems,
Journal of the Chinese Institute of Engineers,
Vol.21, No. 3, pp.269-282, 1998. (SCI, EI)
- R. M. Haralick, A. K. Somani, C. Wittenbrink, R.
Johnson, K. Cooper,L. G. Shapiro, I. T. Phillips, J. N. Hwang, W.
Cheung, Y.H. Yao, C. H. Chen, L. Yang, B.
Daugherty, B. Lorbeski, K. Loving, T. Miller, L. Parkins, et. al.
Proteus: A Reconfigurable
Computational Network for Computer Vision,
Journal of Machine Vision and Applications,
Vol. 8, No. 2, pp. 85-100, March 1995. (SCI, EI)
- P. D. Stigall and C. -H. Chen,
A Performance Simulation
of Local Area Networks Using CSMA/CD and Token Bus Protocols,
Computers & Electrical Engineering,
Vol. 16, No.3, 1990. (SCI, EI)
B. International Conference Paper (47)
- Hsu-Yao Huang, Chi-Yuan Huang, and Chung-Ho
Chen,
Tile-Based GPU
Optimizations through ESL Full System Simulation,
in the IEEE International Symposium on Circuits and Systems
(ISCAS),
May 20-23, 2012, Seoul, Korea.
- Chen-Chieh Wang, Sheng-Hsin Lo, Yao-Ning Liu, and Chung-Ho
Chen,
NetVP: A System-Level
NETwork Virtual Platform for Network Accelerator Development,
in the IEEE International Symposium on Circuits and Systems
(ISCAS),
May 20-23, 2012, Seoul, Korea.
- Chen-Chieh Wang and Chung-Ho Chen,
An Optimized
Cryptographic Processing Unit for IPsec Processors,
in the 26th International Technical Conference on
Circuits/Systems, Computers and Communications (ITC-CSCC),
June 19-22, 2011, Gyeongju, Korea.
- Kuan-Chung Chen and Chung-Ho Chen,
A Synchronization
Profiler for Hybrid Full System Simulation Platform,
in the International SoC Design Conference (ISOCC-2010),
Nov. 22-23, 2010, Incheon, Korea.
- Xie-Zeng Shen, Shin-Ying Lee, and Chung-Ho
Chen,
Full System Simulation
with QEMU: an Approach to Multi-View 3D GPU Design,
in the IEEE International Symposium on Circuits and Systems
(ISCAS) ,
May 30 - June 2, 2010, Paris, France.
- Jing-Wun Lin, Chen-Chieh Wang, Chin-Yao Chang, Chung-Ho
Chen , and Kuen-Jong Lee,
Full System Simulation
and Verification Framework,
in the Proceedings of the Fifth International Conference on
Information Assurance and Security (IAS-2009) ,
August 18-20, 2009, Xi'an, China.
- Chen-Chieh Wang, Ro-Pun Wong, Jing-Wun Lin, and Chung-Ho
Chen,
System-Level Development
and Verification Framework for High-Performance System Accelerator,
in the IEEE International Symposium on VLSI Design,
Automation & Test (VLSI-DAT) ,
April 27-30, 2009, Hsinchu, Taiwan.
- Yi-Cheng Lin, Yi-Ying Tsai, Kuen-Jong Lee,
Cheng-Wei Yen, Chung-Ho Chen,
A Software-Based Test
Methodology for Direct-Mapped Data Cache,
in the IEEE Seventeenth Asian Test Symposium (ATS) ,
November 24-27, 2008, Sapporo, Japan.
- Wei-Cheng Lin and Chung-Ho Chen,
Avoiding Unnecessary
Frame Memory Access and Multi-Frame Motion Estimation Computation in
H.264/AVC,
in the IEEE International Symposium on Circuits and Systems
(ISCAS),
May 18-21, 2008, Seattle, Washington, USA.
- Tai-Hua Lu, Chung-Ho Chen , and
Kuen-Jong Lee,
A Hybrid Self-Testing
methodology of Processor Cores,
in the IEEE International Symposium on Circuits and Systems
(ISCAS),
May 18-21, 2008, Seattle, Washington, USA.
- Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho
Chen ,
Address Compression for
Scalable Load/Store Queue Implementation,
in the IEEE International Symposium on Circuits and Systems
(ISCAS),
May 18-21, 2008, Seattle, Washington, USA.
- Tai-Hua Lu, Chung-Ho Chen, and
Kuen-Jong Lee,
A Hybrid Software-Based
Self-Testing methodology for Embedded Processor,
in the ACM Symposium on Applied Computing (SAC),
March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)
- Yi-Ying Tsai, Chia-Jung Hsu, and Chung-Ho
Chen,
Power-efficient and
Scalable Load/Store Queue Design via Address Compression,
in the ACM Symposium on Applied Computing (SAC),
March 16-20, 2008, Fortaleza, Ceara, Brazil. (EI)
- Wei-Cheng Lin and Chung-Ho Chen,
A Data-Reuse Scheme for
Avoiding Unnecessary Frame Buffer Accesses and Display RAM Accesses in
MPEG-4 ASP Video Decoder,
in the IEEE International SoC Conference (SOCC),
September 26-29, 2007, Hsinchu, Taiwan.
- Yi-Cheng Chung, Stanley Lee, and Chung-Ho
Chen,
A Packet Forwarding
Method for the iSCSI Virtualization Switch,
in the 4th International Workshop on Storage Network
Architecture and Parallel I/Os (SNAPI),
September 24, 2007, San Diego, California, USA.
- Wei-Cheng Lin and Chung-Ho Chen,
Reduction of Frame
Memory Accesses and Motion Estimation Computations in MPEG-4 Video
Encoder,
in the 16th International Conference on Computer
Communications and Networks (ICCCN),
August 13-16, 2007, Honolulu, Hawaii, USA.
- Chung-Ho Chen, Yi-Cheng Chung,
Chen-Hua Wang, and Han-Chiang Chen,
Design of a Giga-bit
Hardware Accelerator for the iSCSI Initiator,
in the 31st Annual IEEE Conference on Local Computer
Networks (LCN),
November 14-16, 2006, Tampa, Florida, USA.
- Kuo-Su Hsiao and Chung-Ho Chen,
Scheduler Optimization
by Exploring Wakeup Locality,
in the International Conference of Computer Engineering
& Systems (ICCES),
November 5-7, 2006, Egypt.
- Chung-Ming Chen, Chung-Ho Chen,
Jian-Ping Zeng, and Chao-Tang Yu,
Windows Processing for
Deblocking Filter in H.264/AVC,
in the Proceeding of the 32nd Annual Conference of the IEEE
Industrial Electronics (IECON),
November 7-10, 2006, Paris, France.
- Kuo-Su Hsiao and Chung-Ho Chen,
Improving Scalability
and Complexity of Dynamic Scheduler through Wakeup-Based Scheduling,
in the International Conference of Computer Design,
October, 2006, USA. (EI)
- Wei-Cheng Lin and Chung-Ho Chen,
Exploring Reusable Frame
Buffer Data for MPEG-4 Video Decoding,
in the IEEE International Symposium on Circuits and Systems
(ISCAS),
2006, Island of Kos, Greece. (EI)
- Chung-Ming Chen, Jian-Ping Zeng, Chung-Ho
Chen, Chao-Tang Yu, and Yu-Pin Chang,
Window Architecture for
Deblocking Filter in H.264/AVC,
in the 6th IEEE International Symposium on Signal Processing
and Information Technology,
August 27-30, 2006, Vancouver, Canada. (EI)
- Kuo-Su Hsiao and Chung-Ho Chen,
An Efficient Wakeup
Design for Energy Reduction in High-Performance Superscalar Processors,
in the ACM SIGMicro International Conference on Computing
Frontiers (CF) ,
2005, Italy. (EI)
- Chung-Ming Chen and Chung-Ho Chen,
A Memory Efficient
Architecture for Deblocking Filter in H.264 Using Vertical Processing
Order,
in the IEEE International Conference on Intelligent Sensors,
Sensor Networks, and Information Processing (ISSNIP),
2005, Australia.
- Chung-Ming Chen and Chung-Ho Chen,
Parallel Processing for
Deblocking Filter in H.264/AVC,
in the International Conference on Communications, Internet
and Information Technology (CIIT),
2005, Cambridge, USA. (EI)
- Chung-Ming Chen and Chung-Ho Chen,
Alternative Processing
Order with Efficient Architecture for Adaptive Deblocking Filter in
H.264/AVC,
in the International Conference on Communications, Internet,
and Information Technology (CIIT),
2005, Cambridge, USA. (EI)
- Chung-Ming Chen and Chung-Ho Chen,
An Efficient
Architecture for Deblocking Filter in H.264/AVC Video Coding,
in the International Conference on Computer Graphics and
Imaging (CGIM),
2005, Honolulu, Hawaii, USA. (EI)
- Chung-Ming Chen and Chung-Ho Chen,
An Efficient VLSI
Architecture for Edge Filtering in H.264/AVC,
in the International Conference on Circuits, Signals, and
Systems,
2005, Marina del Rey, CA, USA.
- F.-M Huang and C.-H. Chen,
Memory Access Scheduling
and Bank Precharge Strategies,
in the poster proceeding of 12 th IEEE International
Symposium on Modeling, Analysis, and Simulation of Computer and
Telecommunication Systems,
2004, Netherlands.
- Wei-Cheng Lin and Chung-Ho Chen,
An Energy-Delay
Efficient Power Management Scheme for Embedded System in Multimedia
Applications,
in Proceedings of The IEEE Asia Pacific Conference on
Circuit & System (APCCAS),
2004, Taiwan. (EI)
- N.-Y. Ker, and C.-H. Chen,
An Effective SDRAM Power
Mode Management Scheme for Performance and Energy Sensitive Embedded
Systems,
in the Proceeding of Asia and South Pacific Design
Automation Conference (ASP-DAC) ,
2003, Japan.
- M.-C. Chen, I.–J. Huang, and C.-H. Chen,
Parameterized MAC Unit
Implementation,
in the Proceeding of Asia and South Pacific Design
Automation Conference,
2001, Japan.
- C.-H. Chen, M. -.H Sheu, M.-D.
Shieh, T.-S, Li, and M.-T. Chen,
Design and
Implementation of a 10/100 Mbps Ethernet Switching Hub Controller,
in the Proceeding of the IEEE Asia Pacific Conference on
Communications,
1998, Singapore.
- Ming-Hwa Sheu, Chung-Ho Chen,
Ming-Der Shieh and Tzung-Shiue Li,
A High Performance VLSI
Architecture Design for 10M /100Mbps Ethernet Switching Fabric,
in the Proceeding of International Conference on Consumer
Electronics,
1998, USA. (EI)
- C. -H. Chen and A. Wu,
Microarchitecture
Support for Improving the Performance of Load Target Prediction,
in the Proceeding of 30 th Annual IEEE/ACM International
Symposium on Microarchitecture,
December 1-3, 1997, Research Triangle Park, NC, USA. (EI)
- C. -H. Chen and A. Wu,
An Enhanced DLX-based
Superscalar System Simulator,
in the 3rd Annual Workshop on Computer Architecture Education,
February, 1997, San Antonio, Texas, USA.
- C. -H. Chen and A. Wu,
An Enhanced DLX-based
Superscalar System Simulator,
in the IEEE Computer Architecture Newsletter,
pp.25-31, September, 1997.
- C. -H. Chen and A. K. Somani,
A Unified Architectural
Tradeoff Methodology,
in the Proceeding of the 21st International Symposium on
Computer Architecture,
pp. 348-357, April 18-21, 1994, Chicago, USA. 國科會甲種研究獎 (EI)
- C. -H. Chen and A. K. Somani,
A Cache Protocol for
Error Detection and Recovery in Fault-Tolerant Computing Systems,
in the 24 th International Symposium on Fault-Tolerant
Computing,
pp. 278-287, June 15-17, 1994, Austin Texas, USA. 國科會甲種研究獎 (EI)
- R. M. Haralick, Y-H, Yao, L. G. Shapiro, I. T.
Phillips, A. K. Somani, J. N. Hwang, M. Harrington, C. Wittenbrink, C.
-H. Chen, X. Liu, and S. Chen,
Proteus: Control and
Management System,
in the Proceedings of Workshop on Computer Architectures for
Machine Perception,
pp. 101-108, December 15-17, 1993, New Orleans, USA.
- C. -H. Chen and A. K. Somani,
Error Detection and
Recovery in Fault-Tolerant Processor Systems Using Caches,
in Proceeding of the ISMM International Conference on
Parallel and Distributed Computing and Systems,
pp. 388-393, 1992, Pittsburgh, PA, USA.
- C. -H. Chen and A. K. Somani,
Fault-Tolerant Parallel
Processing with Real-Time Error Detection and Recovery,
in Proceeding of the 26th Asilomar Conference on Signals,
Systems & Computers,
pp. 994-998, 1992, USA.
- C. -H. Chen and A. K. Somani,
Effects of Cache
Traffics on Shared-Bus Multiprocessor Systems,
in Proceedings of the International Conference on Parallel
Processing,
pp. I285-I288, 1992, USA. (EI)
- Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R.
Cooper-K. Shapiro-L-G. Phillips-I-T. Hwang-J-N. Cheung-W. Yao-Y-H. Chen-C-H
. Yang-L. Daugherty-B. Lorbeski-B. Loving-K.
Miller-T. Parkins-L. Soos-S.
Proteus: a
reconfigurable computational network for computer vision,
Published by: IEEE Comput. Soc. Press. In Proceedings. 11th IAPR
International Conference on Pattern Recognition.
pp. 43-54, The Hague, Netherlands, 1992. (Judged among the 6 best
papers).
- Haralick-R-M. Somani-A-K. Wittenbrink-C. Johnson-R.
Cooper-K. Shapiro-L-G. Phillips-I-T. Jenq-Neng-Hwang. Cheung-W.
Yung-Hsi-Yao. Chung-Ho-Chen . Yang-L. Duagherty-B.
Lorbeski-B. Loving-K. Miller-T. Parkins-L. Soos-S.
Proteus: a
reconfigurable computational network for computer vision,
in Proceedings of the SPIE - The International Society for Optical
Engineering, vol.1659. pp. 54-76. 1992. Conf. Title: Image Processing
and Interchange: Implementation and Systems, San Jose, CA, USA. SPIE.
IS\&T. 12-14 Feb. 1992. (EI)
- C. M. Wittenbrink, A. K. Somani, and C.
-H. Chen,
Cache Write Generate for
High Performance Parallel Processing,
Abstract presented in the 19 th International Symposium on
Computer Architecture,
1992, USA. (EI)
- A. K. Somani, C. Wittenbrink, R. M. Haralick, L. G.
Shapiro, J. N. Hwang, C. -H. Chen, R. Johnson, and
K. Cooper,
Proteus System
Architecture and Organization,
in the Proceeding of the Fifth International Parallel
Processing Symposium,
pp. 287-294, 1991.
C. Local Conference Paper (8)
- Yi-Ying Tsai, Ke-Jia Lee, and Chung-Ho
Chen,
Code Compression
Architecture for Memory Bandwidth Optimization in Embedded Systems,
in the Proceeding of the International Computer Symposium
(ICS),
2006, Taiwan.
- Po-Kai Chan, Chung-Ho Chen, and
Cheng-Yeh Yu,
An iWARP-Based TCP/IP
Offload Engine,
in the Proceeding of the 17th VLSI Design/CAD Symposium,
August 8-11, 2006.
- W.-Z. Lin, and C.-H. Chen,
10/100/1000 Mbps
Ethernet MAC with Clock Management for AMBA System,
in the Proceeding of the 13th VLSI Design/CAD Symposium,
2002.
- 盧偉聖、陳中和、蔡宜穎、林宇峰,
特效光源之數位控制核心技術之研製,
in the Proceeding of Taiwan Power Electronic Conference,
2002.
- C.-H. Chen, M.-D. Shieh, and
Jimmy Shou,
VLSI Architecture of an
Instruction-Based Crypto Coprocessor,
in the Proceeding of the 11th VLSI Design/CAD Symposium,
2000.
- 伍麗樵 , 黃胤傅 , 陳中和 , 陳惠淳 , 陳世仁 ,
陳肇男 , 方志強 ,
Download On Demand
多媒體影片租借系統之實作 ,
第 15 屆全國技術及職業教育研討會論文集,
pp. 171-179, 2000.
- S.-H. Sheu, C.-H. Chen, and
T.-S Li,
The Shared Bus
Architecture Design and Chip Implementation for a 10M /100Mbps Ethernet
Switching Fabric,
in the Proceeding of the 8th VLSI Design/CAD Symposium,
1997.
- J.-S. Lin, C.-H. Chen , C.-Y.
Lin, and S.-H. Liu,
The Application of Fuzzy
Hopfield Neural Network for Vector Quantization in Image Compression,
in the Proceeding of the fifth National Conference on Fuzzy
Theory and Application,
pp.66-71, 1997.
D. 專書 (參考著作)
- 嵌入式系統設計 - 以 ARM
處理器基礎之 SOC 平台，
黃悅民、陳敬、侯廷偉、 陳中和 、黃慶祥、林志敏編著。
ISBN 986-7287-63-0 滄海書局， March 2006.
獲評選為優良教科書，教育部顧問室通訊科技人才培育先導型計畫寬頻網際網路組，
台顧字第 0950179468 號 。
- TCP/IP 通訊協定 (
第三版 ) ，
陳中和 、王振傑譯。
The McGraw-Hill Companies Inc.,
ISBN-13: 978-986-157-321-2, Nov. 2006.
- 計算機組織與設計 ( 第三版 )
，
(by D. A. Patterson and J. L. Hennessy)，陳中和 譯。
台灣東華書局，ISBN 957-483-325-9，July 2005.
- TCP/IP 協定 ( 第二版 )，
陳中和、吳秀峰譯。
The McGraw-Hill Companies Inc., ISBN 957-493-812-3, Nov. 2003.
- 微電腦結構，
陳中和 編著，
東大圖書公司 , ISBN 957-19-2684-1, 2002.
- 微電腦實習，
陳中和 編著，
東大圖書公司 , ISBN 957-19-2683-3, 2002.
- TCP/IP 協定，
陳中和、吳秀峰譯。
The McGraw-Hill Companies Inc., ISBN 957-493-435-7, Sept. 2001.
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